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參數(shù)資料
| 型號： | TCS59SM804BFT-70 |
| 廠商： | Toshiba Corporation |
| 英文描述： | 16M×4Banks×4Bits Synchronous DRAM(4組16M×4位同步動態(tài)RAM) |
| 中文描述： | 1,600 × 4Banks × 4Bits同步DRAM（4組1,600 × 4位同步動態(tài)RAM）的 |
| 文件頁數(shù)： | 34/49頁 |
| 文件大?。?/td> | 2423K |
| 代理商： | TCS59SM804BFT-70 |
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TC59SM816/08/04BFT/BFTL-70,-75,-80
2000-03-14 34/49
1-13 Self Refresh Entry command
(RAS
=
L, CAS
=
L, WE
=
H, CKE
=
L, BS0, BS1, A0~A12
=
Don’t care)
The Self Refresh Entry command is used to enter Self Refresh mode. While the device is in Self Refresh
mode, all input and output buffers (except the CKE buffer) are disabled and the Refresh operation is
automatically performed. Self Refresh mode is exited by taking CKE “high” (the Self Refresh Exit
command).
1-14 Self Refresh Exit command
(CKE
=
H, CS
=
H or CKE
=
H, RAS
=
H, CAS
=
H)
This command is used to exit from Self Refresh mode. Any subsequent commands can be issued after
t
RC
from the end of this command.
1-15 Clock Suspend Mode Entry/Power Down Mode Entry command
(CKE
=
L)
The internal CLK is suspended for one cycle when this command is issued (when CKE is asserted
“l(fā)ow”). The device state is held intact while the CLK is suspended. On the other hand, when the device is
not operating the Burst cycle, this command performs entry into Power Down mode. All input and output
buffers (except the CKE buffer) are turned off in Power Down mode.
1-16 Clock Suspend Mode Exit/Power Down Mode Exit command
(CKE
=
H)
When the internal CLK has been suspended, operation of the internal CLK is resumed by providing
this command (asserting CKE “high”). When the device is in Power Down mode, the device exits this
mode and all disabled buffers are turned on to the active state. Any subsequent commands can be issued
after one clock cycle from the end of this command.
1-17 Data Write/Output Enable, Data Mask/Output Disable command
(DQM
=
L/H or LDQM, UDQM
=
L/H)
During a Write cycle, the DQM or LDQM, UDQM signal functions as Data Mask and can control every
word of the input data. During a Read cycle, the DQM or LDQM, UDQM signal functions as the control
of output buffers.
The LDQM signal controls DQ0~DQ7 and the UDQM signal controls DQ8~DQ15.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TCS59SM804BFT-75 | 16M×4Banks×4Bits Synchronous DRAM(4組16M×4位同步動態(tài)RAM) |
| TCS59SM804BFT-80 | 16M×4Banks×4Bits Synchronous DRAM(4組16M×4位同步動態(tài)RAM) |
| TCS59SM804BFTL-70 | 16M×4Banks×4Bits Synchronous DRAM(4組16M×4位同步動態(tài)RAM) |
| TCS59SM804BFTL-75 | 16M×4Banks×4Bits Synchronous DRAM(4組16M×4位同步動態(tài)RAM) |
| TCS59SM804BFTL-80 | 16M×4Banks×4Bits Synchronous DRAM(4組16M×4位同步動態(tài)RAM) |
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