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參數(shù)資料
| 型號： | TCM320AC37PT |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | VOICE-BAND AUDIO PROCESSORS VBAPE |
| 中文描述： | 語音頻帶音頻處理器VBAPE |
| 文件頁數(shù)： | 10/23頁 |
| 文件大小： | 317K |
| 代理商： | TCM320AC37PT |
TCM320AC36, TCM320AC37
VOICE-BAND AUDIO PROCESSORS (VBAP
)
SLWS003C – MAY 1992 – REVISED APRIL – 1998
10
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
timing requirements
clock timing requirements over recommended ranges of supply voltage and operating free-air temperature
(see Figure 1 through Figure 4)
MIN
NOM
MAX
UNIT
tt
Transition time, CLK and DCLKX/DCLKR
10
ns
Duty cycle, CLK
45%
50%
55%
Duty cycle, DCLKX/DCLKR
All typical values are at VCC = 5 V, TA = 25
°
C.
transmit timing requirements over recommended ranges of supply voltage and operating free-air
temperature, fixed-data-rate mode (see Figure 2)
45%
50%
55%
MIN
MAX
UNIT
tsu(FSX)
th(FSX)
Setup time, FSX high before CLK
↓
Hold time, FSX high after CLK
↓
20
468
ns
20
468
ns
receive timing requirements over recommended ranges of supply voltage and operating free-air
temperature, fixed-data-rate mode (see Figure 1)
MIN
MAX
UNIT
tsu(FSR)
th(FSR)
tsu(DIN)
th(DIN)
Setup time, FSR high before CLK
↓
Hold time, FSR high after CLK
↓
Setup time, DIN high or low before CLK
↓
Hold time, DIN high or low after CLK
↓
20
468
ns
20
468
ns
20
ns
20
ns
transmit timing requirements over recommended ranges of supply voltage and operating free-air
temperature, variable-data-rate mode (see Figure 4)
MIN
MAX
UNIT
tsu(FSX)
th(FSX)
Setup time, FSX high before DCLKX
↓
Hold time, FSX high after DCLKX
↓
40
tc(DCLKX)–40
tc(DCLKX)–35
ns
35
ns
receive timing requirements over recommended ranges of supply voltage and operating free-air
temperature, variable-data-rate mode (see Figure 3)
MIN
MAX
UNIT
tsu(FSR)
th(FSR)
tsu(DIN)
th(DIN)
Setup time, FSR high before DCLKR
↓
Hold time, FSR high after DCLKR
↓
Setup time, DIN high or low before DCLKR
↓
Hold time, DIN high or low after DCLKR
↓
40
ns
35
tc(DCLKR)–35
ns
30
ns
30
ns
switching characteristics
propagation delay times over recommended ranges of operating conditions, fixed-data-rate mode,
C
L
= 0 to 10 pF (see Figure 2)
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
tpd1
tpd2
tpd3
tpd4
tpd5
From CLK bit 1 high to DOUT bit 1 valid
35
ns
From CLK high to DOUT valid, bits 2 to n
35
ns
From CLK bit n low to DOUT bit n Hi-Z
30
ns
From CLK bit 1 high to TSX active (low)
Rpullup = 1.24 k
Rpullup = 1.24 k
40
ns
From CLK bit n low to TSX inactive (high)
30
ns
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