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參數(shù)資料
| 型號(hào)： | TC94A29FAG |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封裝： | 10 X 10 MM, 0.50 MM PITCH, PLASTIC, LQFP-64 |
| 文件頁數(shù)： | 18/20頁 |
| 文件大?。?/td> | 273K |
| 代理商： | TC94A29FAG |
TC94A29FAG/FB
2003-04-01
7
Pin
No.
Symbol
Pin Name
Function and Operation
Remarks
64
P5-0/S9
I/O port 5-0
/LCD segment output
1
2
3
P5-1/S10
/BCK
(BRK3)
P5-2/S11
/LRCK
(BRK4)
P5-3/S12
/AOUT
(BRK5)
I/O port 5
/LCD segment output
/CD processor
function
4
5
6
7
P6-0/S13
/ADin1
/DOUT
(BRK6)
P6-1/S14
/ADin2
/IPF
(BRK7)
P6-2/S15
/ADin3
/SBOK
(BRK8)
P6-3/S16
/ADin4
/CLCK
(BRK9)
I/O port 6
/LCD segment output
/CD processor
function
●BCK: Bit clock output pin. One of three
frequencies, 32, 48 or 64 can be
specified using a CD command.
At normal speed: 32 fs = 1.4112 MHz
●LRCK: LR channel clock output pin. For the L
channel, this pin drives a low level. For
the R channel, it drives a high level.
The polarity can be inverted using a
CD command.
At normal speed: 44.1 kHz
●AOUT: Audio data output pin. Either MSB first
or LSB first can be specified using a
CD command.
●DOUT: Digital data output pin. It drives data at
up to double speed (complying with
CP-1201).
●IPF:
Correction flag output pin. If the AOUT
output is C2 error detection/correction,
a high level appears to indicate an
uncorrectable symbol. (Also called
C2PO)
●SBOK: CRCC test result output pin for
subcode Q data. A high level appears
when the data has passed the test.
●CLCK: Clock input/output pin for reading
subcode P to W data. The input/output
polarity can be inverted using a CD
command.
●DATA: Subcode P to W data output pin.
●SFSY: Frame sync signal output pin for
playback.
●SBSY: Block sync signal output pin for
subcode. When a subcode sync is
detected, a high level appears at S1.
The controller enables CD interrupts.
When an interrupt occurs on the falling
edge of the SBSY signal, the program
jumps to address 2.
(Note) Interrupts should not be enabled when
CD processor operation is undefined.
P6-0 to P6-3 pins have multiplexed functions for
the on-chip 6-bit 4-channel AD converter analog
input. The on-chip AD converter uses
successive approximation. The conversion time
is 242
ms when the 16.9344-MHz crystal
oscillator is used and 7 instruction cycles
(280
ms) when the 75-kHz crystal oscillator is
used. The program can specify necessary pins
for AD analog input on a per bit basis. The
internal power supply (MVDD) is used as the
reference voltage. When the P6-0 to P6-3 pins
are used as I/O port input, each pin can be
pulled up or down by program.
(Continued on next page)
MVDD
Input
instruction
LCD
voltage
MVDD
Input
instruction
Release
enable
LCD
voltage
MVDD
Input
instruction
Release
enable
LCD
voltage
RIN1
MVSS
MVDD
AD input
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參數(shù)描述 |
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| TC94A29FB | 制造商:TOSHIBA 制造商全稱:Toshiba Semiconductor 功能描述:TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic |
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