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參數(shù)資料
| 型號： | TC94A04AFG |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP60 |
| 封裝： | 14 X 14 MM, 0.80 MM PITCH, PLASTIC, QFP-60 |
| 文件頁數(shù)： | 7/42頁 |
| 文件大?。?/td> | 701K |
| 代理商： | TC94A04AFG |
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TC94A04AFG/AFDG
2005-09-28
15
3.2
Control Commands Description
Each command explanation is shown below. *mark in each command explanation table shows the
initial value at the time of reset.
Command-40h (0100 0000): TIMING (4400h*)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
SYPD
SYD1
SYD0
0
SYPA
SYA1
SYA0
0
SYPS
SYS1
SYS0
0
ELROS
EBC-
OS1
EBC-
OS0
Bit
Name
Description
Value
Operation
D15
Fixed to 0 (zero)
0
ASP program starts on falling edge
D14
SYPD
ASP digital block sync polarity
switching
1*
ASP program starts on rising edge
0*
Signal after SYNC 1 fs output
1
Signal after SYNC 2 fs output 2 fs (for 96 kHz sampling)
2
SYNC pin
D13
D12
SYD
[1:0]
ASP digital block SYNC signal
input switching
3
ELRI/O pin
D11
Fixed to 0 (zero)
0
DF-processing starts in a falling
D10
SYPA
DF block sync polarity
switching
1*
DF-processing starts in a rising
0*
SYNC 1 fs output
1
SYNC 2 fs output
2
Reserved
D9
D8
SYA
[1:0]
DF block sync input switching
3
Reserved
D7
Fixed to 0 (zero)
0*
Reference input
= L Lch
D6
SYPS
SYNC circuit input polarity
switching (SYNC reference
signal)
1
Reference input
= H Lch
0*
Internal divided results
1
SYNC pin
2
ELRI/O pin
D5
D4
SYS
[1:0]
SYNC circuit input switching
(SYNC reference signal)
3
Output ELRI/O pin input divided by 2 (for 96 kHz sampling)
D3
Fixed to 0 (zero)
0*
1 fs (Internal fs)
D2
ELROS
Select the clock at the time of
ELRI/O output
1
2 fs (Internal fs
× 2)
0*
32 fs (Internal fs
× 32)
1
64 fs (Internal fs
× 64)
2
128 fs (Internal fs
× 128)
D1
D0
EBCOS
[1:0]
Select the clock at the time of
EBCI/O output
3
Reserved
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