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參數(shù)資料
| 型號： | TC94A04AF |
| 廠商： | Toshiba Corporation |
| 英文描述： | 1 CHIP AUDIO DIGITAL PROCESSOR |
| 中文描述： | 1芯片音頻數(shù)字處理器 |
| 文件頁數(shù)： | 12/42頁 |
| 文件大?。?/td> | 565K |
| 代理商： | TC94A04AF |
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TC94A04AF/AFD
2001-11-15
12
2.2.2 Setting RAM (sequential)
The RAMs are set by command data using the IFDI signal.
The first byte after the I
2
C address (32h) is a command, which differs for each RAM. The next two bytes contain the start address for each RAM.
The length of the data field following the RAM address bytes is 2
×
n bytes. The address is automatically incremented by 1.
During program running, 1 word of data is written at a time in internal RAM synchronizing with a SYNC signal.
Therefore, when performing continuously two or more write to word, unless it applies more than 1/fs [sec] per 1 word and it sets up, taking in of data is not
performed correctly.
At the time of program STOP, it is written in asynchronous.
CS
IFDI
(MCU
→
)
IFCK
C3
C2
C5
C4
C7
C6
C1
C0
A3
A2
A5
A4
A7
A6
A1
A0
RA3
RA2
RA5
RA4
RA7
RA6
RA1
RA0
Cn: COMMAND
An: I
2
C address
RAn: RAM-ADDRESS
Dn: Data
start
32h
HZ
HZ
HZ
end
RA11
RA10
RA13
RA12
RA15
RA14
RA9
RA8
D11
D10
D13
D12
D15
D14
D9
D8
HZ
HZ
D1
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| TC94A04AFD | 制造商:TOSHIBA 制造商全稱:Toshiba Semiconductor 功能描述:1 CHIP AUDIO DIGITAL PROCESSOR |
| TC94A04AFDG | 制造商:TOSHIBA 制造商全稱:Toshiba Semiconductor 功能描述:1 chip Audio Digital Processor |
| TC94A04AFG | 制造商:TOSHIBA 制造商全稱:Toshiba Semiconductor 功能描述:1 chip Audio Digital Processor |
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| TC94A14F | 制造商:TOSHIBA 制造商全稱:Toshiba Semiconductor 功能描述:Digital Servo Single-Chip Processor for Use in CD Player |
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