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參數(shù)資料
| 型號： | TC9432AF |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP100 |
| 封裝： | 14 X 20 MM, 0.65 MM PITCH, PLASTIC, QFP-100 |
| 文件頁數(shù)： | 10/16頁 |
| 文件大?。?/td> | 251K |
| 代理商： | TC9432AF |
TC9432AF
2002-10-21
3
Pin Function
Pin No.
Symbol
I/O
Functional Description
Remarks
1
TEST0
I
Test mode terminal. Normally, keep at open.
With pull-up resistor.
2
HSO
O
3
UHSO
O
Playback speed mode flag output terminal.
UHSO
HSO
Playback
Speed
H
Normal
H
L
2 times
L
H
4 times
L
―
4
EMPH
O
Subcode Q data emphasis flag output terminal.
Emphasis ON at “H” level and OFF at “L” level. The output
polarity can invert by command.
―
5
LRCK
O
Channel clock output terminal. (44.1 kHz)
L-ch at “L” level and R-ch at “H” level. The output polarity
can invert by command.
―
6
VSS
―
Digital GND terminal.
―
7
BCK
O
Bit clock output terminal. (1.4112 MHz)
―
8
AOUT
O
Audio data output terminal.
―
9
DOUT
O
Digital data output terminal.
―
10
MBOV
O
Buffer memory over signal output terminal. Over at “H”
level.
―
11
IPF
O
Correction flag output terminal.
At “H” level, AOUT output is made to correction
impossibility by C2 correction processing.
―
12
SBOK
O
Subcode Q data CRCC check adjusting result output
terminal. The adjusting result is OK at “H” level.
―
13
CLCK
I/O
Subcode P~W data readout clock input/output terminal.
This terminal can select by command bit.
Schmit input.
14
VDD
―
Digital power supply voltage terminal.
―
15
VSS
―
Digital GND terminal.
―
16
DATA
O
Subcode P~W data output terminal.
―
17
SFSY
O
Play-back frame sync signal output terminal.
―
18
SBSY
O
Subcode block sync signal output terminal.
―
19
SPCK
O
Processor status signal readout clock output terminal.
―
20
SPDA
O
Processor status signal output terminal.
―
21
COFS
O
Correction frame clock output terminal.
(7.35 kHz)
―
22
MONIT
O
Internal signal (DSP internal flag and PLL clock) output
terminal. Selected by command.
―
23
VDD
―
Digital power supply voltage terminal.
―
24
TESIO0
I
Test input/output terminal. Normally, keep at “L” level.
―
25
P2VREF
―
PLL double reference voltage supply terminal.
―
26
HSSW
O
2/4 times speed at “VREF” voltage.
2-state output.
(PVREF, HiZ)
27
ZDET
O
1bit DA converter zero detect flag output terminal.
―
28
PDO
O
Phase difference signal output terminal of EFM signal and
PLCK signal.
3-state output.
(P2VREF, PVREF, VSS)
29
TMAXS
O
TMAX detection result output terminal. Selected by
command bit (TMPS).
3-state output.
(P2VREF, PVREF, VSS)
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