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參數(shù)資料
| 型號(hào)： | TC9331F |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP80 |
| 封裝： | 14 X 20 MM, 0.80 MM PITCH, PLASTIC, QFP-80 |
| 文件頁數(shù)： | 8/31頁 |
| 文件大小： | 791K |
| 代理商： | TC9331F |
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TC9331F
2002-02-05
16
(2-2) Control register 1 (CNT-R1)
(*: Default value)
Bit
Symbol
Function
0*
Prohibit
7
PCMON
The program counter values are output at terminals IO15～I(xiàn)O7. (The
external RAM is placed on standby.)
1
Run
0*
Prohibit
6
ACMP
When the CRAM or OFRAM pointer values coincide with the rewrite
counter address, data in both RAM are rewritten.
1
Run
0*
XI = 640 fs
5
CKSL
Selects the XI oscillation (input) clock frequency.
1
XI = 512 fs
0*
PSRAM
4
PS
Selects the externally attached RAM type (PSRAM or DRAM).
1
DRAM
―
3
―
Not assigned.
―
0*
High priority 16 bit
(DB16)
2
DSL
Selects the internal DBUS data that will access the externally attached
RAM source (high priority 16/32 bit).
1
32 bit (DB32)
0*
16 bit/access (IO16)
1
IOS
Selects an 8 bit or a 16 bit access mode for the external RAM source.
1
8 bit/access (IO8)
0*
Prohibit
0
XSEP
Partitions the externally attached RAM into delay and data table
domains.
1
Run
(2-3) Control register 0 (CNT- R0) (Note 1)
(*: Default value)
Bit
Symbol
Function
0*
On
7
PRGALL
The active switch is turned to the “on” position when the program is
loaded. During this active state, instructions are placed in an NOP
condition. When the switch is turned from the “on” position to the “off”
position, the XINT and RMRF ignore flags are reset.
1
Off
0*
Off
6
BRKRQ
Once the program break address (BRKA) has been established,
setting BRKRQ to “1” will activate the break.
1
On
0
Mute off
5
INMT
Sets the SDI0 and SDI1 terminal input to “0” mute.
1*
Mute on
0
Mute off
4
OUTMT2
Sets the SDO2 terminal output to “0” mute.
1*
Mute on
0
Mute off
3
OUTMT1
Sets the SDO1 terminal output to “0” mute.
1*
Mute on
0
Mute off
2
OUTMT0
Sets the SDO0 terminal output to “0” mute.
1*
Mute on
0*
Trigger off
1
XCLR
Trigger bit that clears the externally attached RAM delay domain to
“0”. Once the clearing operation has been initiated, the bit is reset to a
trigger “off” position (XCLR = 0).
1
Trigger on
0
Standby off
0
XSTBY
Places the externally attached RAM on standby.
1*
Standby on
Note 1: The CNT-RO data is latched via a SYNC signal.
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