參數(shù)資料
型號: TC9204-DS-R04
廠商: Electronic Theatre Controls, Inc.
英文描述: 4-Port 10/100/1000 Smart Ethernet Switch
中文描述: 4端口10/100/1000智能以太網(wǎng)交換機
文件頁數(shù): 9/49頁
文件大?。?/td> 1549K
代理商: TC9204-DS-R04
TC9204M
Preliminary Data Sheet
Pin Listing
(continued)
No.
101 NC
102 NC
103 NC
104 NC
105 Gtxck
Pin label
Type
NA
NA
NA
NA
I
Description
Reserved for future use
Reserved for future use
Reserved for future use
Reserved for future use
The 125Mhz reference clock for 1000Mbps operating mode. This clock is
used as a reference clock for the GMII transmission clock for every port.
Digital +2.0V power supply for core
I/O
pd
The led can signal either filtering of broadcast frames. Also the led
remains lit if the POST test fails, which indicates a faulty chip.
O
The led is lit whenever a unicast packets overflow condition is reached
and some frames are dropped by the buffer management engine.
G
Digital ground for core
I
The 25Mhz system clock.
I
pus
General reset. Active Low.
I/O
pd
GMII transmit data - most significant bit
I/O
pd
GMII transmit data - bit 6
I/O
pd
GMII transmit data - bit 5
O
GMII transmit data - bit 4
GMII/MII transmit data - bit 3
I/O
pd
Priority bandwidth configuration pins.
PriBndw(1)is latched on reset
P
Digital +2.0V power supply for core
GMII/MII transmit data - bit 2
I/O
pu
Priority bandwidth configuration pins. These configuration pins allow the
bandwidth percentage assigned to a priority packet queue to be modified
to certain hardwired levels. PriBndw chooses between 4 hardwired
spreading percentage schemes among the 4 priority queues of each port.
PriBndw(0)is latched on reset
GMII/MII transmit data - bit 1
PriClass[2] is latched on reset
Priority class - most significant bit.
GMII/MII transmit data - least significant bit
I/O
pu
Priority class - least significant bit. Sets priority level per port basis.
PriClass[2] - '00' - port 2 low priority
PriClass[2] - '01' - port 2 has normal priority
PriClass[2] - '10' - port 2 has high priority
PriClass[2] - '11' - port 2 has very high priority
PriClass[2] is latched on reset
O
GMII/MII transmit enable
O
GMII transmit clock
G
Digital ground for core
I/O
pd
Transmit Error
I
MII transmit clock
I
s
MII carrier sense indication
106 Vdd 2.0
107 BcstLED
P
108 OvUnLED
109 Vss 2.0
110
Sysck
111
Reset
112
Txd27
113
Txd26
114
Txd25
115
Txd24
Txd23
116
PriBndw1
117
118
Vdd 2.0
Txd22
PriBndw0
Txd21
119
priclass21
Txd20
priclass20
I/O
pd
120
121 Txen2
122 Gtxclk2
123 Vss 2.0
124 Txer2
125 Txclk2
126 Crs2
Confidential.
Copyright
2003, IC Plus Corp.
9/49
July 29, 2003
TC9204M-DS-R05
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