參數(shù)資料
型號: TC74VHCT00AFK
廠商: Toshiba Corporation
英文描述: Quad 2-Input NAND Gate
中文描述: 四2輸入與非門
文件頁數(shù): 2/9頁
文件大?。?/td> 250K
代理商: TC74VHCT00AFK
TC74VHCT00AF/AFN/AFT/AFK
2007-10-17
2
Pin Assignment
IEC Logic Symbol
Truth Table
A
B
Y
L
L
H
L
H
H
H
L
H
H
H
L
Absolute Maximum Ratings (Note 1)
Characteristics
Symbol
Rating
Unit
Supply voltage range
V
CC
0.5 to 7.0
V
DC input voltage
V
IN
0.5 to 7.0
V
0.5 to 7.0
(Note 2)
DC output voltage
V
OUT
0.5 to V
CC
+
0.5
(Note 3)
V
Input diode current
I
IK
20
mA
Output diode current
I
OK
±
20
(Note 4)
mA
DC output current
I
OUT
±
25
mA
DC V
CC
/ground current
I
CC
±
50
mA
Power dissipation
P
D
180
mW
Storage temperature
T
stg
65 to 150
°C
Note 1: Exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in IC performance or
even destruction.
Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the
significant change in temperature, etc.) may cause this product to decrease in the reliability significantly
even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute
maximum ratings and the operating ranges.
Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook
(“Handling Precautions”/“Derating Concept and Methods”) and individual reliability data (i.e. reliability test
report and estimated failure rate, etc).
Note 2: V
CC
=
0 V
Note 3: High or low state. I
OUT
absolute maximum rating must be observed.
Note 4: V
OUT
<
GND, V
OUT
>
V
CC
(4)
(5)
(9)
(10)
2A
2B
&
3A
3B
(12)
(13)
4A
4B
(6)
(8)
(11)
2Y
3Y
4Y
(1)
(2)
1A
1B
(3)
1Y
V
CC
9
4B
4A
4Y
8
14
13
12
11
10
1A
1
2
3
4
5
6
7
2A
2B
2Y
GND
3B
3A
3Y
(top view)
1B
1Y
相關(guān)PDF資料
PDF描述
TC74VHCT00AFT CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC QUAD 2-INPUT NAND GATE
TC74VHCT04AFK CERAMIC CHIP/MIL-PRF-55681
TC74VHCT04AF CERAMIC CHIP/MIL-PRF-55681
TC74VHCT04AFN CERAMIC CHIP/MIL-PRF-55681
TC74VHCT04AFT CERAMIC CHIP/MIL-PRF-55681
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