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參數(shù)資料
| 型號(hào)： | TC74LCX273FW |
| 廠商： | Toshiba Corporation |
| 英文描述： | Low-Voltage Octal D-Type Flip-Flop with Clear with 5-V Tolerant Inputs and Outputs |
| 中文描述： | 低電壓八路D類觸發(fā)器與Clear翻牌5 V容限輸入和輸出 |
| 文件頁數(shù)： | 4/10頁 |
| 文件大?。?/td> | 183K |
| 代理商： | TC74LCX273FW |
TC74LCX273F/FW/FT
2002-01-11
4
Electrical Characteristics
DC Characteristics
(Ta 40 to 85°C)
Characteristics
Symbol
Test Condition
V
CC
(V)
Min
Max
Unit
H-level
V
IH
2.7 to 3.6
2.0
Input voltage
L-level
V
IL
2.7 to 3.6
0.8
V
I
OH
= 100 A
2.7 to 3.6
V
CC
0.2
I
OH
= 12 mA
2.7
2.2
I
OH
= 18 mA
3.0
2.4
H-level
V
OH
V
IN
V
IH
or V
IL
I
OH
= 24 mA
3.0
2.2
I
OL
= 100 A
2.7 to 3.6
0.2
I
OL
= 12 mA
2.7
0.4
I
OL
= 16 mA
3.0
0.4
Output voltage
L-level
V
OL
V
IN
V
IH
or V
IL
I
OL
= 24 mA
3.0
0.55
V
Input leakage current
I
IN
V
IN
0 to 5.5 V
2.7 to 3.6
5.0
A
Power-off leakage current
I
OFF
V
IN
/V
OUT
5.5 V
0
10.0
A
V
IN
V
CC
or GND
2.7 to 3.6
10.0
Quiescent supply current
I
CC
V
IN
3.6 to 5.5 V
2.7 to 3.6
10.0
Increase in Icc per input
I
CC
V
IN
V
CC
0.6 V
2.7 to 3.6
500
A
AC Characteristics
(Ta 40 to 85°C)
Characteristics
Symbol
Test Condition
V
CC
(V)
Min
Max
Unit
2.7
Maximum clock frequency
f
MAX
(Figure 1, Figure 2)
3.3 0.3
150
MHz
2.7
9.5
Propagation delay time (CK-Q)
t
PLH
t
PHL
(Figure 1, Figure 2)
3.3 0.3
1.5
8.5
ns
2.7
9.5
Propagation delay time (
CLR
-Q)
t
PHL
(Figure 1, Figure 3)
3.3 0.3
1.5
8.5
ns
2.7
3.3
Minimum pulse width (CK)
t
w (H)
t
w (L)
(Figure 1, Figure 2)
3.3 0.3
3.3
ns
2.7
3.3
Minimum pulse width (
CLR
)
t
w (L)
(Figure 3)
3.3 0.3
3.3
ns
2.7
2.5
Minimum setup time
t
s
(Figure 1, Figure 2)
3.3 0.3
2.5
ns
2.7
1.5
Minimum hold time
t
h
(Figure 1, Figure 2)
3.3 0.3
1.5
ns
2.7
2.5
Minimum removal time
t
rem
(Figure 4)
3.3 0.3
2.0
ns
2.7
Output to output skew
t
osLH
t
osHL
(Note 10)
3.3 0.3
1.0
ns
Note 10: Parameter guaranteed by design.
(t
osLH
|t
pLHm
t
pLHn
|, t
osHL
|t
pHLm
t
pHLn
|)
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