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參數(shù)資料
| 型號： | TC74HC40105AP |
| 廠商： | Toshiba Corporation |
| 英文描述： | 4 Bit 】 16 Word FIFO Register |
| 中文描述： | 4位】16字FIFO寄存器 |
| 文件頁數(shù)： | 4/11頁 |
| 文件大?。?/td> | 474K |
| 代理商： | TC74HC40105AP |
TC74HC40105AP/AF
2007-10-01
4
Functional Description
(1)
Writing data
Data can be written into the FIFO whenever DIR is high and a low to high transition occurs on the
SI pin.
DIR will toggle momentarily until the data has been transferred to the second word register.
SI must be toggled before the next 4-bit word can be written. The first and subsequent words will
automatically ripple to the output end of the device even if there is not a full 16 words of input data.
When all 16 words are filled with data, DIR will go low and additional data cannot be written into the
device.
Reading data
When a data word appears in the sixteenth data register (just before the output buffer), DOR goes
high and, if
OE
is low, data can be output on the high to low transition of
SO
.
The data remaining in the registers now ripples to the next higher word position opening the first
word position for new data. DIR goes high and additional data can be written in. During the output of
data, DOR toggles momentarily after each read. When the data registers become empty, DOR goes
low and
SO
is ignored.
Master rest
When a high is input to MR, the internal control logic is initialized. This causes DIR to go high and
DOR to go low. The contents of the data registers are not changed, but are invalid and will be written
over when the first word is loaded.
Cascading
The TC74HC40105A can be cascaded to form longer registers simply by connecting DOR of the first
device to SI of the second and DIR of the second device to
SO
of the first. Additional devices may be
cascaded by repeating the above. Of course, the Qn outputs of the first device must be connected to
the Dn inputs of the second.
In this mode, an MR pulse must be applied after the supply voltage is turned on. For words wider
than 4-bits, the DIR and DOR outputs from each FIFO must be ANDed respectively and the SI and
SO
inputs must each be paralleled.
(2)
(3)
(4)
Absolute Maximum Ratings (Note 1)
Characteristics
Symbol
Rating
Unit
Supply voltage range
V
CC
0.5 to 7
V
DC input voltage
V
IN
0.5 to V
CC
+
0.5
V
DC output voltage
V
OUT
0.5 to V
CC
+
0.5
V
Input diode current
I
IK
±
20
mA
Output diode current
I
OK
±
20
mA
(DIR, DOR)
DC output current
(Q0 to Q3)
I
OUT
±
25
±
35
mA
DC V
CC
/ground current
I
CC
±
75
mA
Power dissipation
P
D
500 (DIP) (Note 2)/180 (SOP)
mW
Storage temperature
T
stg
65 to 150
°C
Note 1: Exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in IC performance or
even destruction.
Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the
significant change in temperature, etc.) may cause this product to decrease in the reliability significantly
even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute
maximum ratings and the operating ranges.
Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook
(“Handling Precautions”/“Derating Concept and Methods”) and individual reliability data (i.e. reliability test
report and estimated failure rate, etc).
Note 2: 500 mW in the range of Ta
=
40 to 65°C. From Ta
=
65 to 85°C a derating factor of
10 mW/°C shall be
applied until 300 mW.
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