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參數(shù)資料
| 型號(hào)： | TC74ACT74P_07 |
| 廠(chǎng)商： | Toshiba Corporation |
| 英文描述： | CMOS Digital Integrated Circuit Silicon Monolithic Dual D-Type Flip Flop with Preset and Clear |
| 中文描述： | CMOS數(shù)字集成電路硅單片雙D類(lèi)拖鞋與預(yù)置和清除 |
| 文件頁(yè)數(shù)： | 4/10頁(yè) |
| 文件大小： | 280K |
| 代理商： | TC74ACT74P_07 |
TC74ACT74P/F/FN/FT
2007-10-01
4
Electrical Characteristics
DC Characteristics
Test Condition
Ta = 25°C
Ta =
40 to 85°C
Characteristics
Symbol
V
CC
(V)
Min
Typ.
Max
Min
Max
Unit
High-level input
voltage
V
IH
―
4.5
to
5.5
2.0
―
―
2.0
―
V
Low-level input
voltage
V
IL
―
4.5
to
5.5
―
―
0.8
―
0.8
V
High-level output
voltage
V
OH
V
IN
= V
IH
or
V
IL
I
OH
=
50
μ
A
I
OH
=
24 mA
I
OH
=
75 mA
(Note)
4.5
4.5
5.5
4.4
3.94
―
4.5
―
―
―
―
―
4.4
3.80
3.85
―
―
―
V
Low-level output
voltage
V
OL
V
IN
= V
IH
or
V
IL
I
OL
= 50
μ
A
I
OL
= 24 mA
I
OL
= 75 mA
(Note)
4.5
4.5
5.5
―
―
―
0.0
―
―
0.1
0.36
―
―
―
―
0.1
0.44
1.65
V
Input leakage
current
I
IN
V
IN
= V
CC
or GND
5.5
―
―
±0.1
―
±1.0
μ
A
I
CC
V
IN
= V
CC
or GND
5.5
―
―
4.0
―
40.0
μ
A
Quiescent supply
current
I
C
Per input: V
IN
= 3.4 V
Other input: V
CC
or GND
5.5
―
―
1.35
―
1.5
mA
Note:
This spec indicates the capability of driving 50
transmission lines.
One output should be tested at a time for a 10 ms maximum duration.
Timing Requirements
(input: t
r
= t
f
= 3 ns)
Test Condition
Ta =
25°C
Ta =
40 to
85°C
Characteristics
Symbol
V
CC
(V)
Limit
Limit
Unit
Minimum pulse width
(CK)
t
w (L)
t
w (H)
―
5.0 ± 0.5
5.0
5.0
ns
Minimum pulse width
(CLR , PR )
t
w (L)
―
5.0 ± 0.5
5.7
6.5
ns
Minimum set-up time
t
s
―
5.0 ± 0.5
3.5
3.5
ns
Minimum hold time
t
h
―
5.0 ± 0.5
1.5
1.5
ns
Minimum removal time
(CLR , PR )
t
rem
―
5.0 ± 0.5
2.0
2.0
ns
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