參數(shù)資料
型號: TC74ACT112P
廠商: Toshiba Corporation
英文描述: CMOS Digital Integrated Circuit Silicon Monolithic Dual J-K Flip Flop with Preset and Clear
中文描述: CMOS數(shù)字集成電路硅單片雙JK觸發(fā)器拖鞋與預(yù)置和清除
文件頁數(shù): 1/9頁
文件大?。?/td> 318K
代理商: TC74ACT112P
TC74ACT112P/F/FN
2007-10-01
1
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC74ACT112P,TC74ACT112F,TC74ACT112FN
Dual J-K Flip Flop with Preset and Clear
The TC74ACT112 is an advanced high speed CMOS DUAL J-K
FLIP FLOP fabricated with silicon gate and double-layer metal
wiring C
2
MOS technology.
It achieves the high speed operation similar to equivalent
Bipolar Schottky TTL while maintaining the CMOS low power
dissipation.
This device may be used as a level converter for interfacing
TTL or NMOS to High Speed CMOS. The inputs are compatible
with TTL, NMOS and CMOS output voltage levels.
In accordance with the logic level given J and K input this
device changes state on negative going transition of the clock
pulse.
CLEAR
and
PRESET
are independent of the clock and
accomplished by a low logic level on the corresponding input.
All inputs are equipped with protection circuits against static
discharge or transient excess voltage.
Features
High speed: f
max
=
175 MHz (typ.) at V
CC
=
5 V
Low power dissipation: I
CC
=
4
μ
A (max) at Ta
=
25°C
Compatible with TTL outputs: V
IL
=
0.8 V (max)
Symmetrical output impedance: |I
OH
|
=
I
OL
=
24 mA (min)
Balanced propagation delays: t
pLH
t
pHL
Pin and function compatible with 74F112
Pin Assignment
V
IH
=
2.0 V (min)
Capability of driving 50
Ω
transmission lines.
Note: xxxFN (JEDEC SOP) is not available in
Japan.
TC74ACT112P
TC74ACT112F
TC74ACT112FN
Weight
DIP16-P-300-2.54A
SOP16-P-300-1.27A
SOL16-P-150-1.27
: 1.00 g (typ.)
: 0.18 g (typ.)
: 0.13 g (typ.)
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