參數(shù)資料
型號: TC74AC377
廠商: Toshiba Corporation
英文描述: dvanced high speed CMOS OCTAL D-TYPE FLIP-FLOP fabricated
中文描述: 先進適用的高速CMOS八進制D型觸發(fā)器捏造
文件頁數(shù): 1/3頁
文件大小: 225K
代理商: TC74AC377
TOSHIBA
TOSHIBA CORPORATION
1/3
TC74AC Series
TC74AC377
The information contained here is subject to change without notice.
The information contained herein is presented only as guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties
which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. These TOSHIBA products are intended for usage in general electronic
equipments (office equipment, communication equipment, measuring equipment, domestic electrification, etc.) Please make sure that you consult with us before you use these TOSHIBA products in equip-
ments which require high quality and/or reliability, and in equipments which could have major impact to the welfare of human life (atomic energy control, spaceship, traffic signal, combustion control, all types
of safety devices, etc.). TOSHIBA cannot accept liability to any damage which may occur in case these TOSHIBA products were used in the mentioned equipments without prior consultation with TOSHIBA.
Features:
High Speed:
Low Power Dissipation:
High Noise Immunity:
Symmetrical Output Impedance:
(min.). Capability of driving 50
Balanced Propagation Delays:
Wide Operating Voltage Range:
Pin and Function Compatible with 74F377
Available in DIP, SOIC and SOP Packages
f
MAX
= 140MHz (typ.) at V
I
CC
V
NIH
= V
CC
= 5V
= 8
μ
A (max.) at T
= 28% V
I
OH
S
= I
transmission lines.
t
pLH
= t
pHL
V
CC
(opr.) = 2V~5.5V
a
= 25
(min.)
= 24mA
°
C
NIL
CC
S
OL
Pin Assignment
The TC74AC377 is an advanced high speed CMOS OCTAL
D-TYPE FLIP-FLOP fabricated with silicon gate and double-
layer metal wiring C
MOS technology.
It achieves the high speed operation similar to equivalent
Bipolar Schottky TTL, while maintaining the CMOS low
power dissipation.
These 8-bit D-type flip-flops are controlled by a clock input
(CK) and a output enable input (G).
The signal level applied to the D inputs are transferred to Q
outputs during the positive going transition of CK.
When the G is high, the eight outputs are in a high imped-
ance state.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
2
Truth Table
X:
Don’t care
IEC Logic Symbol
1
2
3
4
5
6
7
20
19
18
17
16
15
14
V
CC
Q8
D8
D7
Q7
Q6
D6
G
Q1
D1
D2
Q2
Q3
D3
13
D5
8
D4
9
12
Q5
Q4
11
CK
10
GND
(TOP VIEW)
INPUTS
OUTPUT
G
CLOCK
DATA
Q
H
X
X
NO CHANGE
L
L
L
L
H
H
X
X
NO CHANGE
G
CK
D1
D2
D3
D4
D5
D6
D7
D8
(1)
(11)
(3)
(4)
(7)
(8)
(13)
(14)
(17)
(18)
(2)
(5)
(6)
(9)
(12)
(15)
(16)
(19)
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
G1
1C2
2D
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