參數(shù)資料
型號(hào): TC7135CBU
廠商: Microchip Technology Inc.
英文描述: 4-1/2 Digit A/D Converter
中文描述: 4-1/2位A / D轉(zhuǎn)換
文件頁數(shù): 8/13頁
文件大?。?/td> 224K
代理商: TC7135CBU
3-120
TELCOM SEMICONDUCTOR, INC.
TC7135
4-1/2 DIGIT
ANALOG-TO-DIGITAL CONVERTER
Figure 8. Strobe Signal Pulses Low Five Times per Conversion
Figure 7. Timing Diagrams for Outputs
The active-low STROBE pulses aid BCD data transfer
to UARTs, microprocessors, and external latches. (See
Application Note AN-16.)
BUSY Output
At the beginning of the signal-integration phase, BUSY
(pin 21) goes high and remains high until the first clock pulse
after the integrator zero crossing. BUSY returns to logic "0"
after the measurement cycle ends in an overrange condi-
tion. The internal display latches are loaded during the first
clock pulse after BUSY and are latched at the clock pulse
end. The BUSY signal does not go high at the beginning of
the measurement cycle, which starts with the auto-zero
phase.
OVERRANGE Output
If the input signal causes the reference voltage integra-
tion time to exceed 20,000 clock pulses, the OVERRANGE
output (pin 27) is set to logic "1." The OVERRANGE output
register is set when BUSY goes low and reset at the
beginning of the next reference-integration phase.
UNDERRANGE Output
If the output count is 9% of full scale or less (
1800
counts), the UNDERRANGE output (pin 28) register bit is
set at the end of BUSY. The bit is set low at the next signal-
integration phase.
STROBE Output
During the measurement cycle, the STROBE output
(pin 26) control line is pulsed low five times. The five low
pulses occur in the center of the digit drive signals (D
1
, D
2
,
D
3
, D
4
and D
5
; see Figure 8).
D
5
goes high for 201 counts when the measurement
cycles end. In the center of D
5
pulse, 101 clock pulses after
the end of the measurement cycle, the first STROBE occurs
for one-half clock pulse. After D
5
strobe, D
4
goes high for 200
clock pulses. STROBE goes low 100 clock pulses after D
4
goes high. This continues through the D
1
drive pulse.
The digit drive signals will continue to permit display
scanning. STROBE pulses are not repeated until a new
measurement is completed. The digit drive signals will not
continue if the previous signal resulted in an overrange
condition.
INTEGRATOR
OUTPUT
OVERRANGE
WHEN
APPLICABLE
UNDERRANGE
WHEN
APPLICABLE
SYSTEM
ZERO
10,001
COUNTS
FULL MEASUREMENT CYCLE
40,002 COUNTS
SIGNAL
INTE
10,000
COUNTS
(FIXED)
REFERENCE
INTEGRATE
20,001
COUNTS (MAX)
BUSY
EXPANDED SCALE
BELOW
D5
D4
D3
D2
D1
FIRST D5 OF SYSTEM ZERO
AND REFERENCE INTEGRATE
ONE COUNT LONGER.
100
COUNTS
DIGIT SCAN
STROBE
AUTO ZERO
SIGNAL
INTEGRATE
REFERENCE
INTEGRATE
D5
D4
D3
D2
D1
DIGIT SCAN
FOR
OVERRANGE
*
*
*
END OF CONVERSION
D5 (MSD)
DATA
BUSY
B1–B8
STROBE
D5
D4
D3
D2
D1
D4
DATA
D3
DATA
D2
DATA
D1 (LSD)
DATA
D5
DATA
NOTE ABSENCE
OF STROBE
201
COUNTS
200
COUNTS
200
COUNTS
200
COUNTS
200
COUNTS
200
COUNTS
200
COUNTS
*
*
DELAY BETWEEN BUSY GOING LOW AND FIRST STROBE
PULSE IS DEPENDENT ON ANALOG INPUT.
TC7135
OUTPUTS
相關(guān)PDF資料
PDF描述
TC7135CLI 4-1/2 Digit A/D Converter
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TC7135CBU 4-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTER
TC7135CLI 4-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTER
TC7135CPI 4-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTER
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