參數(shù)資料
型號(hào): TC7126ACPL
廠商: TelCom Semiconductor, Inc.
元件分類: 顯示驅(qū)動(dòng)器
英文描述: 3-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTERS
中文描述: 3-1/2數(shù)字模擬數(shù)字轉(zhuǎn)換器
文件頁(yè)數(shù): 8/13頁(yè)
文件大?。?/td> 198K
代理商: TC7126ACPL
3-224
TELCOM SEMICONDUCTOR, INC.
3-1/2 DIGIT
ANALOG-TO-DIGITAL CONVERTERS
TC7126
TC7126A
The TC7126A is a drop-in replacement for the TC7126
and ICL7126 that offers a greatly improved internal refer-
ence temperature coefficient. No external component value
changes are required to upgrade existing designs.
COMPONENT VALUE SELECTION
Auto-Zero Capacitor
(C
AZ
)
The C
AZ
size has some influence on system noise. A
0.33
μ
F capacitor is recommended for 200 mV full-scale
applications where 1 LSB is 100
μ
V. A 0.033
μ
F capacitor is
adequate for 2V full-scale applications. A Mylar-type dielec-
tric capacitor is adequate.
Reference Voltage Capacitor
(C
REF
)
The reference voltage, used to ramp the integrator
output voltage back to zero during the reference integrate
phase, is stored on C
REF
. A 0.1
μ
F capacitor is acceptable
when V
REF–
is tied to analog common. If a large common-
mode voltage exists (V
REF–
analog common) and the
application requires a 200 mV full scale, increase C
REF
to
1
μ
F. Roll-over error will be held to less than 0.5 count. A
Mylar-type dielectric capacitor is adequate.
Integrating Capacitor
(C
INT
)
C
INT
should be selected to maximize integrator output
voltage swing without causing output saturation. Due to
the TC7126A's superior analog common temperature co-
efficient specification, analog common will normally sup-
ply the differential voltage reference. For this case, a
±
2V
full-scale integrator output swing is satisfactory. For 3
readings per second (f
OSC
= 48 kHz), a 0.047
μ
F value is
suggested. For 1 reading per second, 0.15
μ
F is recom-
mended. If a different oscillator frequency is used, C
INT
must be changed in inverse proportion to maintain the
nominal
±
2V integrator swing.
An exact expression for C
INT
is:
(
(
f
OSC
When a segment driver is in-phase with the backplane
signal, the segment is OFF. An out-of-phase segment drive
signal causes the segment to be ON, or visible. This AC drive
configuration results in negligible DC voltage across each
LCD segment, ensuring long LCD life. The polarity segment
driver is ON for negative analog inputs. If V
IN+
and V
IN–
are
reversed, this indicator would reverse.
On the TC7126A, when the TEST pin is pulled to V
+
, all
segments are turned ON. The display reads –1888. During
this mode, LCD segments have a constant DC voltage
impressed. DO NOT LEAVE THE DISPLAY IN THIS MODE
FOR MORE THAN SEVERAL MINUTES; LCDS MAY BE
DESTROYED IF OPERATED WITH DC LEVELS FOR
EXTENDED PERIODS.
The display font and segment drive assignment are
shown in Figure 4.
System Timing
The oscillator frequency is
4
4 prior to clocking the
internal decade counters. The three-phase measurement
cycle takes a total of 4000 counts (16,000 clock pulses).
The 4000-count cycle is independent of input signal magni-
tude.
Each phase of the measurement cycle has the following
length:
(1) Auto-zero phase: 1000 to 3000 counts
(4000 to 12,000 clock pulses)
For signals less than full scale, the auto-zero phase
is assigned the unused reference integrate time
period.
(2) Signal integrate:
1000 counts
(4000 clock pulses)
This time period is fixed. The integration period is:
t
SI
= 4000
,
where f
OSC
is the externally-set clock frequency.
(3) Reference integrate: 0 to 2000 counts
(0 to 8000 clock pulses)
where: f
OSC
= Clock frequency at pin 38
V
FS
= Full-scale input voltage
R
INT
= Integrating resistor
V
INT
= Desired full-scale integrator output swing.
At 3 readings per second, a 750
resistor should be
placed in series with C
INT
. This increases accuracy by
compensating for comparator delay. C
INT
must have low
dielectric absorption to minimize roll-over error. A polypro-
pylene capacitor is recommended.
1
f
OSC
DISPLAY FONT
1000's
100's
10's
1's
Figure 4. Display Font and Segment Assignment
C
INT
=
,
)
(4000)
V
INT
1
V
FS
R
INT
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