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| 型號： | TC7117IPL |
| 元件分類： | ADC |
| 英文描述： | 1-CH DUAL-SLOPE ADC, PDIP40 |
| 封裝： | PLASTIC, DIP-40 |
| 文件頁數(shù)： | 32/32頁 |
| 文件大?。?/td> | 515K |
| 代理商： | TC7117IPL |
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2006 Microchip Technology Inc.
DS21455C-page 9
TC7106/A/TC7107/A
4.0
ANALOG SECTION
In addition to the basic signal integrate and de-
integrate cycles discussed, the circuit incorporates an
auto-zero cycle. This cycle removes buffer amplifier,
integrator, and comparator offset voltage error terms
from the conversion. A true digital zero reading results
without adjusting external potentiometers. A complete
conversion consists of three cycles: an auto-zero,
signal integrate and reference integrate cycle.
4.1
Auto-Zero Cycle
During the auto-zero cycle, the differential input signal
is disconnected from the circuit by opening internal
analog gates. The internal nodes are shorted to analog
common (ground) to establish a zero input condition.
Additional analog gates close a feedback loop around
the integrator and comparator. This loop permits
comparator offset voltage error compensation. The
voltage level established on CAZ compensates for
device offset voltages. The offset error referred to the
input is less than 10
μV.
The auto-zero cycle length is 1000 to 3000 counts.
4.2
Signal Integrate Cycle
The auto-zero loop is entered and the internal differen-
tial inputs connect to VIN+ and VIN-. The differential
input signal is integrated for a fixed time period. The
TC7136/A signal integration period is 1000 clock
periods or counts. The externally set clock frequency is
divided by four before clocking the internal counters.
The integration time period is:
EQUATION 4-1:
The differential input voltage must be within the device
Common mode range when the converter and mea-
sured system share the same power supply common
(ground). If the converter and measured system do not
share the same power supply common, VIN- should be
tied to analog common.
Polarity is determined at the end of signal integrate
phase. The sign bit is a true polarity indication, in that
signals less than 1LSB are correctly determined. This
allows precision null detection limited only by device
noise and auto-zero residual offsets.
4.3
Reference Integrate Phase
The third phase is reference integrate or de-integrate.
VIN- is internally connected to analog common and
VIN+ is connected across the previously charged
reference capacitor. Circuitry within the chip ensures
that the capacitor will be connected with the correct
polarity to cause the integrator output to return to zero.
The time required for the output to return to zero is
proportional to the input signal and is between 0 and
2000 counts.
The digital reading displayed is:
EQUATION 4-2:
5.0
DIGITAL SECTION (TC7106A)
The TC7106A (Figure 5-2) contains all the segment
drivers necessary to directly drive a 3-1/2 digit liquid
crystal display (LCD). An LCD backplane driver is
included. The backplane frequency is the external
clock frequency divided by 800. For three conversions/
second, the backplane frequency is 60Hz with a 5V
nominal amplitude. When a segment driver is in phase
with the backplane signal, the segment is “OFF.” An out
of phase segment drive signal causes the segment to
be “ON” or visible. This AC drive configuration results
in negligible DC voltage across each LCD segment.
This insures long LCD display life. The polarity
segment driver is “ON” for negative analog inputs. If
VIN+ and VIN- are reversed, this indicator will reverse.
When the TEST pin on the TC7106A is pulled to V+, all
segments are turned “ON.” The display reads -1888.
During this mode, the LCD segments have a constant
DC voltage impressed. DO NOT LEAVE THE DIS-
PLAY IN THIS MODE FOR MORE THAN SEVERAL
MINUTES! LCD displays may be destroyed if operated
with DC levels for extended periods.
The display font and the segment drive assignment are
shown in Figure 5-1.
FIGURE 5-1:
Display Font and Segment
Assignment
In the TC7106A, an internal digital ground is generated
from a 6-volt zener diode and a large P channel source
follower. This supply is made stiff to absorb the large
capacitive currents when the backplane voltage is
switched.
TSI =
4
FOSC
x 1000
Where: FOSC = external clock frequency.
1000 =
VIN
VREF
Display Font
1000's
100's
10's
1's
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