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參數(shù)資料
| 型號(hào)： | TC660 |
| 廠商： | TelCom Semiconductor, Inc. |
| 英文描述： | 100mA CHARGE PUMP DC-TO-DC VOLTAGE CONVERTER |
| 中文描述： | 100mA的電荷泵型DC - DC電壓轉(zhuǎn)換器 |
| 文件頁(yè)數(shù)： | 5/8頁(yè) |
| 文件大?。?/td> | 122K |
| 代理商： | TC660 |
4-9
TELCOM SEMICONDUCTOR, INC.
7
6
5
4
3
1
2
8
TC660
100mA CHARGE PUMP DC-TO-DC
VOLTAGE CONVERTER
Figure 1. TC660 Test Circuit (Inverter)
Figure 2. Idealized Switched Capacitor
V+
GND
S3
S1
S2
S4
C2
VOUT = – VIN
C1
Theoretical Power Efficiency
Considerations
In theory, a voltage multiplier can approach 100%
efficiency if certain conditions are met:
(1) The drive circuitry consumes minimal power.
(2) The output switches have extremely low ON
resistance and virtually no offset.
(3) The impedances of the pump and reservoir
capacitors are negligible at the pump frequency.
The TC660 approaches these conditions for negative
voltage multiplication if large values of C
1
and C
2
are used.
Energy is lost only in the transfer of charge between
capacitors if a change in voltage occurs.
The energy lost
is defined by:
E = 1/2 C
1
(V
12
– V
22
)
V
1
and V
2
are the voltages on C
1
during the pump and
transfer cycles. If the impedances of C
1
and C
2
are relatively
high at the pump frequency (refer to Figure 2) compared to
the value of R
L
, there will be a substantial difference in
voltages V
1
and V
2
. Therefore, it is desirable not only to
make C
2
as large as possible to eliminate output voltage
ripple, but also to employ a correspondingly large value for
C
1
in order to achieve maximum efficiency of operation.
1
2
3
4
8
7
6
5
TC660
+
V+
(+5V)
VOUT
C1
150 μF
+
C2
150 μF
IL
RL
IS
V+
Circuit Description
The TC660 contains all the necessary circuitry to com-
plete a voltage inverter (Figure 1), with the exception of two
external capacitors, which may be inexpensive 150
μ
F polar-
ized electrolytic capacitors. Operation is best understood by
considering Figure 2, which shows an idealized voltage
inverter. Capacitor C
1
is charged to a voltage V
+
for the half
cycle when switches S
1
and S
3
are closed. (
Note:
Switches
S
2
and S
4
are open during this half cycle.) During the second
half cycle of operation, switches S
2
and S
4
are closed, with
S
1
and S
3
open, thereby shifting capacitor C
1
negatively by
V
+
volts. Charge is then transferred from C
1
to C
2
, such that
the voltage on C
2
is exactly V
+
, assuming ideal switches and
no load on C
2
.
The four switches in Figure 2 are MOS power switches;
S
1
is a P-channel device, and S
2
, S
3
and S
4
are N-channel
devices. The main difficulty with this approach is that in
integrating the switches, the substrates of S
3
and S
4
must
always remain reverse-biased with respect to their sources,
but not so much as to degrade their ON resistances. In
addition, at circuit start-up, and under output short circuit
conditions (V
OUT
= V
+
), the output voltage must be sensed
and the substrate bias adjusted accordingly. Failure to
accomplish this would result in high power losses and
possible device latch-up. This problem is eliminated in the
TC660 by a logic network which senses the output voltage
(V
OUT
) together with the level translators, and switches the
substrates of S
3
and S
4
to the correct level to maintain
necessary reverse bias.
To improve low-voltage operation, the “LV” pin should
be connected to GND, disabling the internal regulator. For
supply voltages greater than 3.0V, the LV terminal should
be left open to ensure latch-up-proof operation and prevent
device damage.
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