參數(shù)資料
型號: TC55VCM216ASTN55
廠商: Toshiba Corporation
英文描述: TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
中文描述: 馬鞍山暫定東芝數(shù)字集成電路硅柵CMOS
文件頁數(shù): 5/14頁
文件大?。?/td> 201K
代理商: TC55VCM216ASTN55
TC55VCM216ASTN40,55
2002-07-04 5/14
AC CHARACTERISTICS AND OPERATING CONDITIONS
(Ta
=
40° to 85°C, V
DD
=
2.7 to 3.6 V)
READ CYCLE
TC55VCM216ASTN
40
55
SYMBOL
PARAMETER
MIN
MAX
MIN
MAX
UNIT
t
RC
Read Cycle Time
40
55
t
ACC
Address Access Time
40
55
t
CO1
Chip Enable(
1
CE
) Access Time
40
55
t
CO2
Chip Enable(CE2) Access Time
40
55
t
OE
Output Enable Access Time
25
30
t
BA
Data Byte Control Access Time
40
55
t
COE
Chip Enable Low to Output Active
5
5
t
OEE
Output Enable Low to Output Active
0
0
t
BE
Data Byte Control Low to Output Active
5
5
t
OD
Chip Enable High to Output High-Z
20
25
t
ODO
Output Enable High to Output High-Z
20
25
t
BD
Data Byte Control High to Output High-Z
20
25
t
OH
Output Data Hold Time
10
10
ns
WRITE CYCLE
TC55VCM216ASTN
40
55
SYMBOL
PARAMETER
MIN
MAX
MIN
MAX
UNIT
t
WC
Write Cycle Time
40
55
t
WP
Write Pulse Width
30
40
t
CW
Chip Enable to End of Write
35
45
t
BW
Data Byte Control to End of Write
35
45
t
AS
Address Setup Time
0
0
t
WR
Write Recovery Time
0
0
t
ODW
R/W Low to Output High-Z
20
25
t
OEW
R/W High to Output Active
0
0
t
DS
Data Setup Time
20
25
t
DH
Data Hold Time
0
0
ns
Note: t
OD
, t
ODO
, t
BD
and t
ODW
are specified in time when an output becomes high impedance, and are not judged depending on
an output voltage level.
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