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參數(shù)資料
| 型號： | TC35273 |
| 廠商： | Toshiba Corporation |
| 英文描述： | MPEG-4 Audiovisual LSI |
| 中文描述： | 的MPEG - 4視聽大規(guī)模集成電路 |
| 文件頁數(shù)： | 11/23頁 |
| 文件大小： | 237K |
| 代理商： | TC35273 |
MPEG-4 Audiovisual Codec LSI
Preliminary
TC35273
TOSHIBA Confidential
2000-4-27
11/23
Version
0.90
Fig. 4 Write Operation in handshake mode
3.1.2 Synchronized access mode
In this mode, a host CPU accomplishes an access to TC35273 in the specified period without a
handshake. However, when the host CPU accesses to the embedded DRAM in TC35273, it has to
check whether the next access is available or not by checking a status register before the access.
Fig.5 shows the timing diagram of a read operation. A read access starts by asserting both a chip
select signal (/HCS) and a read signal (/RD) (timing (a)). After the specified cycles indicated as Tacs,
the host CPU gets the read data and finishes the read operation by negating both /HCS and /HRD
(timing (b)).
Fig.6 shows the timing diagram of a write operation. A write access starts by asserting both /HCS
and a write signal (/WR) (timing (a)). After the specified cycles, the host CPU finishes the write
operation by negating both /HCS and /HWR (timing (b)).
HADDR
/HWR
HDAT
/HWAIT
/HCS
T
CSS
T
WTAD
T
DTWS
T
DTID
T
RDH
T
RR
T
ADH
T
WTID
T
ADS
T
CSH
(a)
(b)
(c)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TC35274 | TOSHIBA MPEG-4 Video Decoder LSI |
| TC35300BP | DTMF RECEIVER |
| TC35310F | DTMF RECEIVER |
| TC370 | FLIP FLOP QUAD D |
| TC390 | DUAL INTERFACE BUFFERS / DUAL 2-INPUT NAND/AND/OR/NOR / DUAL 4-INPUT AND/NAND WITH EXPANDER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TC35274 | 制造商:TOSHIBA 制造商全稱:Toshiba Semiconductor 功能描述:TOSHIBA MPEG-4 Video Decoder LSI |
| TC3531 | 制造商:TRANSCOM 制造商全稱:TRANSCOM 功能描述:5.8 GHz 1W MMIC |
| TC3532 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:4.9 - 6 GHz 29dBm MMIC |
| TC35321 | 制造商:General Electric Company 功能描述:30A 3P DBL THR SS N1 240V NONFUSE |
| TC3538 | 制造商:TRANSCOM 制造商全稱:TRANSCOM 功能描述:5 - 6 GHz 1W MMIC |
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