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參數(shù)資料
| 型號(hào)： | TC3404VQRRT |
| 元件分類： | ADC |
| 英文描述： | 4-CH 16-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO16 |
| 封裝： | QSOP-16 |
| 文件頁數(shù)： | 9/13頁 |
| 文件大?。?/td> | 81K |
| 代理商： | TC3404VQRRT |
5
TC3404
+1.8V, Low Power, Quad-Input,
16-Bit
∑ – A/D Converter with
a Power Fault Monitor
TC3404-1 3/30/00
2001 Microchip Technology Inc.
DS21413A
GENERAL THEORY OF OPERATION
The TC3404 is a 16-bit sigma-delta A/D converter.It
has two differential single-ended inputs, an analog multi-
plexer, and an early warning power fail detector. The de-
tailed description of the key components of the TC3404 is
outlined below. (Also refer to the A/D Operational Flowchart
on page 10 and the Timing Diagrams in Figures 2 through 5).
A/D Converter Operation
When the TC3404 is not converting, it is in sleep mode
with both the SCLK and SDAT lines high. An A/D conversion
is initiated by a high to low transition on the SCLK line at
which time the internal clock of the TC3404 is started and the
address value (A0 and A1) is internally latched. The address
value steers the analog multiplexer to select the input
channel to be converted. Each additional high to low transi-
tion of SCLK (following the initial SCLK falling edge) and
during the time interval t4 will decrement the conversion
accuracy by one bit and reduce the conversion time by one
half. The time interval t4 is referred to as the resolution
reduction window. The minimum conversion resolution is 10
bits so any more than 6 SCLK transitions during t4 will be
ignored.
After each high to low transition of SCLK, in the t4
interval, the SDAT output is driven high by the TC3404 to
acknowledge that the conversion has been decremented.
When the SCLK returns high or the t4 interval ends, the
SDAT line returns low (see Figure 2). When the conversion
is complete SDAT is driven high. The 3404 now enters sleep
mode and the conversion value can be read as a serial data
word on the SDAT line.
Reading the Data Word
After the conversion is complete and SDAT goes high,
the conversion value can be clocked serially onto the SDAT
line by high to low transitions of the SCLK. The data word is
in two’s compliment format with the sign bit clocked onto the
SDAT line first followed by the MSB and ending in the LSB.
For a 16 bit conversion the data word would consist of a sign
bit followed by 15 magnitude bits, Table 1 shows the data
word versus input voltage for a 16 bit conversion. Note that
the full scale input voltage range is
±(2 REFIN– 1LSB). When
REFOUT is fed back directly to REFIN, an LSB is 73V for a
16 bit convertion, as REFOUT is typically 1.193V.
Figure 3 shows typical SCLK and SDAT waveforms for
16, 12 and 10 bit conversions. Note that any complete
convert and read cycle requires 17 negative edge clock
pulses. The first is the convert command. Then, up to six of
these can occur in the resolution reduction window, t4, to
decrement accuracy. The remaining pulses clock out the
conversion data word.
Table 1. Data Conversion Word vs. Voltage Input
(REFIN = 1.193V)
Data Word
INn+ – INn– (Volts)
0111 1111 1111 1111
2.38596 (Positive Full Scale)
0000 0000 0000 0001
72.8 E – 6
0000 0000 0000 0000
0
1111 1111 1111 1111
–72.8 E – 6
1000 0000 0000 0001
–2.38596 (Negative Full Scale)
1000 0000 0000 0000
Reserved Code
The SCLK input has a filter which rejects any positive or
negative pulse of width less than 50ns to reduce noise. The
rejection width of this pulse can vary between 50ns and
750ns depending on processing parameters and supply
voltage.
Figure 3 shows a truth table for determining the mode of
operation for the TC3404 part by recording the value of
SDAT for SCLK in a high, then low, then high state. For
example, if SCLK goes through a 1-0-1 transition and the
corresponding values of SDAT are 1-1-0, then the SCLK
falling edge started a new data conversion. A 0-1-0 for SDAT
would have indicated a resolution reduction had occurred.
This is useful if the microcontroller has a watchdog reset or
otherwise loses track of where the TC3404 part is in the
conversion and data readout sequence. The microcontroller
can simply transition SCLK until it “finds” a Start Conversion
condition.
Power Fail Detector
The power fail detector is a comparator in which the
inverting input is connected to the internal voltage reference,
the non-inverting input is the PFI pin of the TC3404 and the
PFO pin is the active low, open collector output. This
comparator is suitable as an early warning fail or low battery
indicator. In a typical application, where a voltage regulator
is being used to supply power to a system, the power fail
comparator would monitor the input voltage to the regulator
while the VDD monitor would measure the output voltage of
the regulator. PFO would drive the interrupt pin of a
microcontroller.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TC3404VQRTR | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 1.8V Lw Pwr Quad RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| TC3405 | 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:16-Bit, Low Cost, Low Power Sigma-Delta A/D Converter |
| TC3405A | 制造商:LINER 制造商全稱:Linear Technology 功能描述:Standalone Linear Li-lon Battery Charger with Thermistor Input |
| TC3405VPE | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 16-Bit Sigma-Delta RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| TC3405VQR | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 16-Bit Sigma-Delta RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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