參數(shù)資料
型號： TC2015-3.3VCTTR
廠商： Microchip Technology
文件頁數(shù)： 5/36頁
文件大?。?/td> 0K
描述： IC REG LDO 3.3V .1A SOT23A-5
標(biāo)準(zhǔn)包裝： 3,000
穩(wěn)壓器拓?fù)浣Y(jié)構(gòu)： 正，固定式
輸出電壓： 3.3V
輸入電壓： 最高 6V
電壓 - 壓降（標(biāo)準(zhǔn)）： 0.09V @ 100mA
穩(wěn)壓器數(shù)量： 1
電流 - 輸出： 100mA（最?。?br>
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： SC-74A，SOT-753
供應(yīng)商設(shè)備封裝： SOT-23-5
包裝： 帶卷 (TR)
其它名稱： TC20153.3VCTTR
13
Analog & Interface Product Selector Guide Summer 2012
P
o
W
er
mana
gemen
T:
P
ow
er
mos
Fe
T
d
river
s(
c
ontinued)
P
ar
t#
c
onfiguration
o
perating
Temperature r
ange
(°
c
)
P
eak
o
utput
c
ur
rent
(
a
)
o
utput
r
esistance
(r
h/
r
l)
(m
ax.
W
@
25°
c
)
m
aximum
s
upply
Voltage
(V)
Input/
o
utput
d
ela
y
(t
d1
,t
d2)
(1)
(ns)
P
ackages
low-
s
ide
d
river
s,
2.0
a
to
12.0
a
P
eak
o
utput
c
ur
rent
TC1413
Single,
Inverting
40
to
+85
3
4/4
16
35/35
8-pin
PDIP,
8-pin
SOIC,
8-pin
MSOP
TC1413N
Single,
Non-inverting
40
to
+85
3
4/4
16
35/35
8-pin
PDIP,
8-pin
SOIC,
8-pin
MSOP
TC4423A
Dual,
Inverting
40
to
+125
3
(typ)/4
(typ)
18
40
(typ)/40
(typ)
8-pin
PDIP,
8-pin
SOIC,
8-pin
DFN
TC4424A
Dual,
Non-inverting
40
to
+125
3
(typ)/4
(typ)
18
40
(typ)/40
(typ)
8-pin
PDIP,
8-pin
SOIC,
8-pin
DFN
TC4425A
Dual,
Inverting
and
Non-inverting
40
to
+125
3
(typ)/4
(typ)
18
40
(typ)/40
(typ)
8-pin
PDIP,
8-pin
SOIC,
8-pin
DFN
TC4423
Dual,
Inverting
40
to
+125
3
5/5
18
33/38
8-pin
PDIP,
16-pin
SOIC
(W),
8-pin
DFN
TC4424
Dual,
Non-inverting
40
to
+125
3
5/5
18
33/38
8-pin
PDIP,
16-pin
SOIC
(W),
8-pin
DFN
TC4425
Dual,
Inverting
and
Non-inverting
40
to
+125
3
5/5
18
33/38
8-pin
PDIP,
16-pin
SOIC
(W),
8-pin
DFN
MCP14E3
Dual,
Inverting
40
to
+125
4.0
3.5/3.0
18
55/55
8-pin
PDIP,
8-pin
SOIC,
8-pin
6×5
DFN
MCP14E4
Dual,
Non-inverting
40
to
+125
4.0
3.5/3.0
18
55/55
8-pin
PDIP,
8-pin
SOIC,
8-pin
6×5
DFN
MCP14E5
Dual,
Inverting
and
Non-inverting
40
to
+125
4.0
3.5/3.0
18
55/55
8-pin
PDIP,
8-pin
SOIC,
8-pin
6×5
DFN
MCP1403
Dual,
Inverting
40
to
+125
4.5
3/3.5
18
48/48
8-pin
PDIP,
8-pin
SOIC,
8-pin
6×5
DFN,
16-pin
SOIC
MCP1404
Dual,
Non-inverting
40
to
+125
4.5
3/3.5
18
48/48
8-pin
PDIP,
8-pin
SOIC,
8-pin
6×5
DFN,
16-pin
SOIC
MCP1405
Dual,
Inverting
and
Non-inverting
40
to
+125
4.5
3/3.5
18
48/48
8-pin
PDIP,
8-pin
SOIC,
8-pin
6×5
DFN,
16-pin
SOIC
MCP1406
Single,
Inverting
40
to
+125
6
1.8
(typ)/2.0
(typ)
18
30/30
5-pin
TO-220,
8-pin
PDIP,
8-pin
6×5
DFN,
8-pin
SOIC
MCP1407
Single,
Non-inverting
40
to
+125
6
1.8
(typ)/2.0
(typ)
18
30/30
5-pin
TO-220,
8-pin
PDIP,
8-pin
6×5
DFN,
8-pin
SOIC
TC429
Single,
Inverting
40
to
+85
6
2.5/2.5
18
53/60
8-pin
PDIP,
8-pin
DFN,
8-pin
SOIC
TC4420
Single,
Non-inverting
40
to
+125
6
2.8/2.5
18
55/55
8-pin
PDIP,
8-pin
SOIC,
5-pin
TO-220,
8-pin
DFN
TC4429
Single,
Inverting
40
to
+125
6
2.8/2.5
18
55/55
8-pin
PDIP,
8-pin
SOIC,
5-pin
TO-220,
8-pin
DFN
TC4421
Single,
Inverting
40
to
+125
9
1.4
(typ)/1.7
18
30/33
8-pin
PDIP,
5-pin
TO-220,
8-pin
DFN
TC4421A
Single,
Inverting
40
to
+125
9
1.25
(typ)/1.5
18
38/42
8-pin
PDIP,
8-pin
SOIC,
5-pin
TO-220,
8-pin
6×5
DFN
TC4422
Single,
Non-inverting
40
to
+125
9
1.4
(typ)/1.7
18
30/33
8-pin
PDIP,
5-pin
TO-220,
8-pin
DFN
TC4422A
Single,
Non-inverting
40
to
+125
9
1.25
(typ)/1.5
18
38/42
8-pin
PDIP,
8-pin
SOIC,
5-pin
TO-220,
8-pin
6×5
DFN
TC4451
Single,
Inverting
40
to
+125
12
0.6
(typ)/1.5
18
15/15
8-pin
SOIC,
8-pin
PDIP,
8-pin
6×5
DFN,
5-pin
TO-220,
5-pin
DDPAK
TC4452
Single,
Non-inverting
40
to
+125
12
0.6
(typ)/1.5
18
15/15
8-pin
SOIC,
8-pin
PDIP,
8-pin
6×5
DFN,
5-pin
TO-220,
5-pin
DDPAK
h
igh-
s
ide/
low-
s
ide
d
river
s
TC4626
Single,
Inverting
40
to
+85
1.5
15/10
6
35/45
8-pin
PDIP,
16-pin
SOIC
(W)
TC4627
Single,
Non-inverting
40
to
+85
1.5
15/10
6
35/45
8-pin
PDIP,
16-pin
SOIC
(W)
TC4431
Single,
Inverting
40
to
+85
1.5
10/10
30
62/78
8-pin
PDIP,
8-pin
SOIC
TC4432
Single,
Non-inverting
40
to
+85
1.5
10/10
30
62/78
8-pin
PDIP,
8-pin
SOIC
s
ynchronous
Buck
h
igh-
s
ide
d
river
s
MCP14628
Dual,
Non-inverting
40
to
+85
2
2.5/2.5
5
(V
dd
),36
(Boot
Pin)
18/20
8-pin
SOIC,
8-pin
3×3
DFN
MCP14700
Dual,
Non-inverting
40
to
+125
2
2.5/2.5
5
(V
dd
),36
(Boot
Pin)
25/25
8-pin
SOIC,
8-pin
3×3
DFN
Note
1:
td
1
=
dela
ytime
from
input
low-to-high
transition
to
output
transition.
t
d2
=
dela
ytime
from
input
high-to-low
transition
to
output
transition.
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