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參數資料
| 型號： | TC1322EUART |
| 元件分類： | DAC |
| 英文描述： | SERIAL INPUT LOADING, 10 us SETTLING TIME, 12-BIT DAC, PDSO8 |
| 封裝： | MSOP-8 |
| 文件頁數： | 7/11頁 |
| 文件大小： | 65K |
| 代理商： | TC1322EUART |
5
TC1322-1
6/23/00
TC1322
12-Bit Digital-to-Analog Converter
with Two-Wire Interface
2001 Microchip Technology Inc.
DS21388A
PIN DESCRIPTION
VREF
Input. Voltage Reference Input can range from 0V to
1.2V below VDD.
SDA
Bi-directional. Serial data is transferred on the SMBus
in both directions using this pin. See System Management
Bus Specification rev. 1.0 for timing diagrams.
SCL
Input. SMBus serial clock. Clocks data into and out of
the TC1322. See System Management Bus Specification
rev. 1.0 for timing diagrams.
GND
Input. Ground return for all TC1322 functions.
VOUT
Output. Buffered DAC output voltage. This voltage is a
function of the reference voltage and the contents of the
DATA register. See Functional Description section.
DAC_OUT
Output. Unbuffered DAC output voltage. This voltage is
a function of the reference voltage and the contents of the
DATA register. However, since it is unbuffered, care must be
taken that the pin is connected only to a high impedance
node.
VDD
Input. Positive power supply input. See electrical speci-
fications.
DETAILED DESCRIPTION
The TC1322 is a monolithic 12-bit digital-to-analog
converter that is designed to operate from a single supply
that can range from 2.7V to 5.5V. The DAC consists of a data
register (DATA), a configuration register (CONF), and a
current output amplifier. The TC1322 uses an external
reference which also determines the maximum output volt-
age.
The TC1322 uses a current-steering DAC based on an
array of matched current sources which goes into the
precision resistor that converts the contents of the Data
Register and VREF into an output voltage, VOUT given by:
VOUT = VREF (DATA/ 4096)
Reference Input
The reference pin, VREF, is a buffered high impedance
input and because of this the load regulation of the refer-
ence source need only to be able to tolerate leakage levels
of current (less than 1
A). VREF accepts a voltage range
from 0 to (VDD – 1.2V). Input capacitance is typically around
10 pF.
Output Amplifier
The TC1322 DAC output is buffered with an internal
unity-gain rail-to-rail input/output amplifier with a typical slew
rate of 0.8V/
sec. Maximum full-scale transition settling
time is 10
sec to within ±1/2 LSB when loaded with 1k in
parallel with 100pF.
Standby Mode
The TC1322 allows the host to put it into a low power
(IDD = 0.5A, typical) Standby mode. In this mode, the D/A
convertion is halted. The SMBus port operates normally.
Standby mode is enabled by setting the SHDN bit in the
CONFIG register. The table below summarizes this opera-
tion.
Standby Mode Operation
SHDN Bit
Operating Mode
0
Normal
1
Standby
SMBus Slave Address
The TC1322 is internally programmed to have a default
SMBus address value of 1001 000b. Seven other addresses
are available by custom order (contact factory).
SERIAL PORT OPERATION
The Serial Clock input (SCL) and bi-directional data port
(SDA) form a 2-wire bi-directional serial port for program-
ming and interrogating the TC1322. The following conven-
tions are used in this bus architecture:
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