
7
TC1320-1
6/23/00
TC1320
8-Bit Digital-to-Analog Converter
with Two-Wire Interface
2001 Microchip Technology Inc.
DS21386A
TC1320 Serial Bus Conventions
TERM
EXPLANATION
Transmitter
The device sending data to the bus.
Receiver
The device receiving data from the bus.
Master
The device which controls the bus: initiating
transfers (START), generating the clock, and
terminating transfers. (STOP)
Slave
The device addressed by the master.
Start
A unique condition signaling the beginning of a
transfer indicated by SDA falling (High –Low)
while SCL is high.
Stop
A unique condition signaling the end of a transfer
indicated by SDA rising (Low –High) while SCL is high.
ACK
A Receiver acknowledges the receipt of each byte
with this unique condition. The Receiver drives
SDA low during SCL high of the ACK clock-pulse.
The Master provides the clock pulse for the ACK cycle.
Busy
Communication is not possible because the bus is
in use.
NOT Busy
When the bus is idle, both SDA and SCL will
remain high.
Data Valid
The state of SDA must remain stable during the
High period of SCL in order for a data bit to be
considered valid. SDA only changes state while
SCL is low during normal data transfers.
( See Start and Stop conditions. )
All transfers take place under control of a host, usually
a CPU or microcontroller, acting as the Master, which
provides the clock signal for all transfers.
The TC1320
always operates as a Slave. The serial protocol is illustrated
in Figure 1. All data transfers have two phases; all bytes are
transferred MSB first. Accesses are initiated by a start
condition (START), followed by a device address byte and
one or more data bytes. The device address byte includes
a Read/Write selection bit. Each access must be terminated
by a Stop Condition (STOP). A convention called
Acknowl-
edge (ACK) confirms receipt of each byte. Note that SDA
can change only during periods when SCL is LOW (SDA changes
while SCL is HIGH are reserved for Start and Stop Conditions).
Start Condition (START)
The TC1320 continuously monitors the SDA and SCL
lines for a start condition (a HIGH to LOW transition of SDA
while SCL is HIGH), and will not respond until this condition
is met.
Address Byte
Immediately following the Start Condition, the host must
transmit the address byte to the TC1320. The 7-bit SMBus
address for the TC1320 is 1001000. The 7-bit address
transmitted in the serial bit stream must match for the
TC1320 to respond with an Acknowledge (indicating the
TC1320 is on the bus and ready to accept data). The eighth
bit in the Address Byte is a Read-Write Bit. This bit is a 1 for
a read operation or 0 for a write operation. During the first
phase of any transfer this bit will be set = 0 to indicate that
the command byte is being written.
Acknowledge (ACK)
Acknowledge (ACK) provides a positive handshake
between the host and the TC1320. The host releases SDA
after transmitting eight bits, then generates a ninth clock
cycle to allow the TC1320 to pull the SDA line LOW to
acknowledge that it successfully received the previous eight
bits of data or address.
Data Byte
After a successful ACK of the address byte, the host
must transmit the data byte to be written or clock out the data
to be read. (See the appropriate timing diagrams. ) ACK will
be generated after a successful write of a data byte into the
TC1320.
Stop Condition (STOP)
Communications must be terminated by a stop condi-
tion (a LOW to HIGH transition of SDA while SCL is HIGH).
The Stop Condition must be communicated by the transmit-
ter to the TC1320. NOTE: Refer to Timing Diagrams for
serial bus timing.