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參數(shù)資料
| 型號(hào)： | TC1072-3.3VCH |
| 廠(chǎng)商： | TelCom Semiconductor, Inc. |
| 英文描述： | 50mA CMOS LDO WITH SHUTDOWN, ERROR OUTPUT AND VREF BYPASS |
| 中文描述： | 50mA的CMOS LDO穩(wěn)壓器具有關(guān)斷，錯(cuò)誤輸出和Vref旁路 |
| 文件頁(yè)數(shù)： | 11/12頁(yè) |
| 文件大小： | 126K |
| 代理商： | TC1072-3.3VCH |
TC1073
5
PRELIMINARY INFORMATION
TC1073-01 6/5/97
100mA CMOS LDO WITH SHUTDOWN,
ERROR OUTPUT AND V
REF
BYPASS
The following equation is used to calculate worst case
actualpower dissipation:
P
D
≈
(V
INMAX
– V
OUTMIN
)I
LOADMAX
Where:
P
D
= Worst case actual power dissipation
V
INMAX
= Maximum voltage on V
IN
V
OUTMIN
= Minimum regulator output voltage
I
LOADMAX
= Maximum output (load) current
Equation 1.
The maximum allowable power dissipation (Equation 2)
is a function of the maximum ambient temperature (T
AMAX
),
the maximum allowable die temperature (125
°
C) and the
thermal resistance from junction-to-air (
θ
JA
). SOT-23A-6
packag has a
θ
JA
of approximately 220
°
C/Wattwhen
mounted on a single layer FR4 dielectric copper clad PC
board.
P
D MAX
= (T
JMAX
– T
JMAX)
θ
JA
Where all terms are previously defined.
Equation 2.
Equation 1 can be used in conjunction with Equation 2
to ensure regulator thermal operation is within limits. For
example:
Given:
V
INMAX
= 3.0V
±
10%
V
OUTMIN
= 2.7V
±
0.5V
I
LOAD
= 98mA
T
AMAX
= 55
°
C
Find:
1. Actual power dissipation
2. Maximum allowable dissipation
Actual power dissipation:
P
D
≈
(V
INMAX
– V
OUTMIN
)I
LOADMAX
= [(3.0 x 1.1) – (2.7 x .995)]40 x 10
–3
= 60mW
Maximum allowable power dissipation:
P
DMAX
= (T
JMAX
– T
AMAX
)
θ
JA
= (125 – 55)
220
= 318mW
In this example, the TC1073 dissipates a maximum of
only 60mW; far below the allowable limit of 318mW. In a
similar manner, Equation 1 and Equation 2 can be used to
calculate maximum current and/or input voltage limits. For
example, the maximum allowable V
IN
is found by sustituting
the maximum allowable power dissipation of 318mW into
Equation 1, from which V
INMAX
= 5.9V.
Layout Considerations
The primary path of heat conduction out of the package
is via the package leads. Therefore, layouts having a
ground plane, wide traces at the pads, and wide power
supply bus lines combine to lower
θ
JA
and therefore in-
crease the maximum allowable power dissipation limit.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TC1072-36VCH | 制造商:MICROCHIP 制造商全稱(chēng):Microchip Technology 功能描述:50mA and 100mA CMOS LDOs with Shutdown, ERROR Output and VREF Bypass |
| TC1072-4.0VCH713 | 功能描述:低壓差穩(wěn)壓器 - LDO 50mA LDO RoHS:否 制造商:Texas Instruments 最大輸入電壓:36 V 輸出電壓:1.4 V to 20.5 V 回動(dòng)電壓（最大值）:307 mV 輸出電流:1 A 負(fù)載調(diào)節(jié):0.3 % 輸出端數(shù)量: 輸出類(lèi)型:Fixed 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-20 |
| TC10724.0VCT713 | 制造商:MICROCHIP 制造商全稱(chēng):Microchip Technology 功能描述:50mA and 100mA CMOS LDOs with Shutdown, ERROR Output and VREF Bypass |
| TC1072-40VCH | 制造商:MICROCHIP 制造商全稱(chēng):Microchip Technology 功能描述:50mA and 100mA CMOS LDOs with Shutdown, ERROR Output and VREF Bypass |
| TC1072-5.0VCH | 制造商:TELCOM 制造商全稱(chēng):TelCom Semiconductor, Inc 功能描述:50mA CMOS LDO WITH SHUTDOWN, ERROR OUTPUT AND VREF BYPASS |
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