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參數(shù)資料
| 型號： | TB62705CPG |
| 廠商： | Marktech Optoelectronics |
| 英文描述： | 8-BIT SHIFT REGISTER, LATCHES & CONSTANT-CURRENT DRIVERS |
| 中文描述： | 8位的移位寄存器，鎖存 |
| 文件頁數(shù)： | 2/15頁 |
| 文件大?。?/td> | 1003K |
| 代理商： | TB62705CPG |
TB62705CPG/CFG/CFNG
2005-10-06
2
BLOCK DIAGRAM
TIMING DIAGRAM
Note:
Latches are level-sensitive, not rising edge-sensitive, and are not synchronized with the CLOCK signal. The
data will pass through the latch circuit if the latch input is set at “H” level, and will be retained if the input is
set at “L”.
OUTn
OUTn
OUTn
SERIAL-IN
LATCH
CLOCK
OUT0
OUT1
OUT3
SERIAL-OUT
ENABLE
OUT7
5 V
0 V
5 V
0 V
5 V
0 V
5 V
0 V
Off
On
Off
On
Off
On
Off
5 V
0 V
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