參數(shù)資料
型號(hào)： TB1308FG
元件分類： 信號(hào)分離
英文描述： SYNC SEPARATOR IC, PQFP48
封裝： 10 X 14 MM, 0.80 MM PITCH, PLASTIC, QFP-48
文件頁數(shù)： 6/33頁
文件大?。?/td> 660K
代理商： TB1308FG
TB1305FG, TB1308FG
2007-07-11
14
Sync separation level
The sync separation level is changed according to the ratio of H-sync width to one line and the connected resistance.
Typical sync separation levels for each format are as follows. Then, VGA-SEP=1 for VGA to UXGA.
HV-SEP = 0 (LOW)
HV-SEP = 1 (HIGH)
Format
R = 1.2 k
R = 1.5 k
R = 1.8 k
R = 1.2 k
R = 1.5 k
R = 1.8 k
625/50i
22
28
33
24
32
37
525/60i
22
28
34
24
31
37
625/50p
22
28
34
25
31
38
525/60p
21
27
32
24
30
36
1125/50i
31
39
45
40
49
54
1125/60i
26
33
39
34
43
50
750/50p
29
37
43
37
46
52
750/60p
24
31
37
32
40
47
1250/50i
25
32
37
32
41
47
1125/50p
36
45
51
45
54
58
1125/60p
31
39
45
39
49
55
VGA/60
15
19
23
16
21
25
SVGA/60
15
18
22
16
20
24
XGA/60
17
22
26
19
24
28
SXGA/60
27
33
39
30
37
43
Unit [%] ; where 286 mVp-p sync for 525/60i and 300 mVp-p sync for others
For “Sync on G” signal, HD-OUT is not output during V-sync period because there is no H-sync during V-sync period.
Furthermore, for Sync on G of XGA input, HD-OUT disappears during active video period caused by unexpected lock of
the internal V-BLK.
The format detection and sync separation performances are changed due to the separation level set by HV-SEP,
VGA-SEP setting and/or the connected resistance with SYNC-IN pin. The careful evaluations are required to set the
separation level under consideration of expected input conditions such as a suppressed sync input, an input with V-sag
and APL (Average Picture Level) fluctuations.
Note on Sync input pin
If the AC-coupling circuit is put before the SYNC-IN pin, the picture on the screen may be not stable. This is because
the sync separation circuit is unable to follow the DC level fluctuation caused by APL (Average Picture Level) change in
the input signal, and the HD and/or VD output is unable to synchronize the input.
It is recommended to input signals via the DC-coupling buffer if necessary.
For the DC level fluctuation caused by APL change, the sync separation ability may be improved to change the
setting of HV-SEP, VGA-SEP and/or changing the resister R. Furthermore, adding a high-resistance around several
M
between SYNC-IN pin and GND (or Vcc) may improve the sync separation ability.
Adding DC restoration circuit such as a clamp circuit can be also effective for the improvement of DC level fluctuation.
Also, refer to Sync separation level descriptions.
相關(guān)PDF資料
PDF描述
TB1308FG SYNC SEPARATOR IC, PQFP48
TB1305FG SYNC SEPARATOR IC, PQFP48
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