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參數(shù)資料
| 型號(hào)： | TB1251CN |
| 廠商： | Toshiba Corporation |
| 英文描述： | PAL/NTSC/SECAM 1 Chip (IF + VCD processor) IC |
| 中文描述： | PAL / NTSC制式/ SECAM制式1片（中頻光碟處理器）芯片 |
| 文件頁(yè)數(shù)： | 26/80頁(yè) |
| 文件大?。?/td> | 1935K |
| 代理商： | TB1251CN |
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TB1251CN
2001-03-06 26/80
Acknowledge
Data Transmit Format 1
Data Transmit Format 2
Data Received Format
At the moment of the first acknowledge, the master transmitter becomes a master receiver and the slave receiver
becomes a slave transmitter. This acknowledge is still generated by the slave.
The Stop condition is generated by the master.
Optional Data Transmit Format: Automatic Increment Mode
In this transmission methods, data is set on automatically incremented sub-address from the specified
sub-address.
Purchase of TOSHIBA I
2
C components conveys a license under the Philips I
2
C Patent Rights to use these
components in an I
2
C system, provided that the system conforms to the I
2
C Standard Specification as defined by
Philips.
7 bit
8 bit
8 bit
S: Start condition
MSB
A: Acknowledge
MSB
P: Stop condition
MSB
S
Slave address
0 A
Sub address
A
Transmit data
A P
S
Slave address
0 A
Sub address
A
Transmit data 1
A
------
------
Sub address
A
Transmit data n
A P
7 bit
8 bit
MSB
MSB
S
Slave address
1 A
Received data 01
A
Received data 02
A P
7 bit
7 bit
8 bit
MSB
MSB
MSB
S
Slave address
0 A 1
Sub address
A
Transmit data 1
------
Transmit data n
A P
8 bit
MSB
SDA by
Transmitter
S
Clock pulse for acknowledgment
9
8
1
The transmitter releases the SDA line (high)
during the acknowledge clock pulse.
The receiver has to pull down the
SDA line (low) during the
acknowledge clock pulse.
SDA by
Receiver
SCL from
Master
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