參數(shù)資料
型號(hào)： TAS5716PAPR
廠商： TEXAS INSTRUMENTS INC
元件分類(lèi)： 音頻／視頻放大
英文描述： 20.6 W, 2 CHANNEL, AUDIO AMPLIFIER, PQFP64
封裝： 10 X 10 MM, GREEN, PLASTIC, HTQFP-64
文件頁(yè)數(shù)： 39/64頁(yè)
文件大小： 1398K
代理商： TAS5716PAPR
CLOCK CONTROL REGISTER (0x00)
DEVICE ID REGISTER (0x01)
SLOS569 – JANUARY 2009............................................................................................................................................................................................... www.ti.com
In the manual mode, the clock control register provides a way for the system microprocessor to update the data
and clock rates based on the sample rate and associated clock frequencies. In the auto-detect mode, the clocks
are automatically determined by the TAS5716. In this case, the clock control register contains the auto-detected
clock status as automatically detected (D7–D2). Bits D7–D5 select the sample rate. Bits D4–D2 select the MCLK
frequency. Bit D0 is used in manual mode only. In this mode, when the clocks are updated a 1 must be written to
D0 to inform the DAP that the written clocks are valid.
Table 3. Clock Control Register (0x00)
D7
D6
D5
D4
D3
D2
D1
D0
FUNCTION
0
–
fS = 32-kHz sample rate
0
1
–
fS = 38-kHz sample rate
0
1
0
–
fS = 44.1-kHz sample rate
0
1
–
–
–
fS = 48-kHz sample rate
(1)
1
0
–
fS = 88.2-kHz sample rate
1
0
1
–
fS = 96-kHz sample rate
1
0
–
fS = 176.4-kHz sample rate
1
–
fS = 192-kHz sample rate
–
0
–
MCLK frequency = 64 × fS
(2)
–
0
1
–
MCLK frequency = 128 × fS
(3)
–
0
1
0
–
MCLK frequency = 192 × fS
–
0
1
–
MCLK frequency = 256 × fS
(1)
–
1
0
–
MCLK frequency = 384 × fS
(4)
–
1
0
1
–
MCLK frequency = 512 × fS
(4)
–
1
0
–
Reserved
–
1
–
Reserved
–
0
–
Bit clock (SCLK) frequency = 64 × fS or 32 × fS (selected in register 0x04)
(1)
–
1
–
Bit clock (SCLK) frequency = 48 × fS
(5)
–
–
–
0
Clock not valid (in manual mode only)(1)
–
1
Clock valid (in manual mode only)
(1)
Default values are in bold.
(2)
Rate not available for 32-KHz data rate or in AM avoidance mode
(3)
Rate not available for 32-kHz data rate
(4)
Rate not available for 176.4-kHz and 192-kHz data rates
(5)
Rate only available for 192-fS and 384-fS MCLK frequencies
The device ID register contains the ID code for the firmware revision.
Table 4. General Status Register (0x01)
D7
D6
D5
D4
D3
D2
D1
D0
FUNCTION
0
–
Default(1)
–
0
1
0
1
0
Identification code
(1)
Default values are in bold.
44
Copyright 2009, Texas Instruments Incorporated
Product Folder Link(s): TAS5716
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