參數(shù)資料
型號: TAS5716PAP
廠商: TEXAS INSTRUMENTS INC
元件分類: 音頻/視頻放大
英文描述: 20.6 W, 2 CHANNEL, AUDIO AMPLIFIER, PQFP64
封裝: 10 X 10 MM, GREEN, PLASTIC, HTQFP-64
文件頁數(shù): 46/64頁
文件大小: 1398K
代理商: TAS5716PAP
INTERCHANNEL DELAY REGISTERS (0x11, 0x12, 0x13, 0x14, 0x15, 0x16)
OFFSET REGISTER (0x17)
SLOS569 – JANUARY 2009............................................................................................................................................................................................... www.ti.com
Internal PWM Channels 1, 2, 3, 4, 5, and 6 are mapped into registers 0x11, 0x12 ,0x13, 0x14, 0x15, and 0x16.
Table 14. Channel Interchannel Delay Register Format
BITS DEFINITION
D7
D6
D5
D4
D3
D2
D1
D0
FUNCTION
Minimum absolute delay, 0 DCLK cycles, default for
0
channel 0(1)
0
1
0
Maximum positive delay, 31 × 4 DCLK cycles
1
0
Maximum negative delay, –32 × 4 DCLK cycles
0
Unused bits
A
SUBADDRESS
D7
D6
D5
D4
D3
D2
D1
D0
Delay = (value) × 4 DCLKs
0x11
0
1
0
1
0
Default value for channel 1 (1)
19
0x12
0
1
0
1
0
Default value for channel 2(1)
13
0x13
0
1
0
Default value for channel 3 (1)
7
0x14
0
1
0
1
0
Default value for channel 4 (1)
25
0x15
1
0
1
0
Default value for channel 5 (1)
–12
0x16
1
0
1
0
Default value for channel 6 (1)
-28
(1)
Default values are in bold.
The offset register is mapped into 0x17.
Table 15. Channel Offset Register Format
D7
D6
D5
D4
D3
D2
D1
D0
FUNCTION
0
Minimum absolute offset, 0 DCLK cycles, default for channel 0(1)
1
Maximum absolute offset, 255 DCLK cycles
(1)
Default values are in bold.
50
Copyright 2009, Texas Instruments Incorporated
Product Folder Link(s): TAS5716
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