www.ti.com............................................................................................................................................................................................... SLOS605 – JANUARY 2009
Power Loss Sequence (AD BTL)
Use the following sequence to powerdown an AD BTL device and its supplies in case of sudden power loss
when time does not permit a controlled shutdown:
1. Assert PDN = 0 and wait at least 2ms then assert HIZ = 0 and wait at least 4
s.
2. Assert RESET = 0.
3. Drive digital inputs low and ramp down PVCC/AVCC supply as follows:
Drive all digital inputs low after RESET has been low for at least 2
s.
Ramp down PVCC/AVCC while ensuring that it remains above 10V until RESET has been low
for at least 2
s.
4. Ramp down AVDD/DVDD while ensuring that it remains above 3V until PVCC/AVCC is below 7.5V
and observing absolute maximum ratings for digital inputs.
Table 2. Serial Control Interface Register Summary(1)
NO. OF
INITIALIZATION
SUBADDRESS
REGISTER NAME
CONTENTS
BYTES
VALUE
A u indicates unused bits.
0x00
Clock control register
1
Description shown in subsequent section
0x6C
0x01
Device ID register
1
Description shown in subsequent section
0x70
0x02
Error status register
1
Description shown in subsequent section
0x00
0x03
System control register 1
1
Description shown in subsequent section
0xA0
0x04
Serial data interface
1
Description shown in subsequent section
0x05
register
0x05
System control register 2
1
Description shown in subsequent section
0x40
0x06
Soft mute register
1
Description shown in subsequent section
0x00
0x07
Master volume
1
Description shown in subsequent section
0xFF (mute)
0x08
Channel 1 vol
1
Description shown in subsequent section
0x30 (0 dB)
0x09
Channel 2 vol
1
Description shown in subsequent section
0x30 (0 dB)
0x0A
Fine master volume
1
Description shown in subsequent section
0x00 (0 dB)
0x0B - 0X0D
1
Reserved(2)
0x0E
Volume configuration
1
Description shown in subsequent section
0x91
register
0x0F
1
Reserved(2)
0x10
Modulation limit register
1
Description shown in subsequent section
0x02
0x11
IC delay channel 1
1
Description shown in subsequent section
0xAC
0x12
IC delay channel 2
1
Description shown in subsequent section
0x54
0x13
IC delay channel 3
1
Description shown in subsequent section
0xAC
0x14
IC delay channel 4
1
Description shown in subsequent section
0x54
0x15-0x19
1
Reserved(2)
0x1A
Start/stop period register
1
0x0F
0x1B
Oscillator trim register
1
0x82
0x1C
BKND_ERR register
1
0x02
0x1D–0x1F
1
Reserved(2)
0x20
Input MUX register
4
Description shown in subsequent section
0x0001 7772
0x21
Ch 4 source select register
4
Description shown in subsequent section
0x0000 4303
0x22 -0X24
4
Reserved(2)
0x25
PWM MUX register
4
Description shown in subsequent section
0x0102 1345
0x26-0x28
4
Reserved(2)
(1)
"ae" stands for
∝ of energy filter, "aa" stands for ∝ of attack filter and "ad" stands for ∝ of decay filter and 1- ∝ = ω.
(2)
Reserved registers should not be accessed.
Copyright 2009, Texas Instruments Incorporated
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