SLOS606D – MARCH 2009 – REVISED SEPTEMBER 2009............................................................................................................................................. www.ti.com
10. This completes the initialization sequence. From this step on, no further constraints are imposed on PDN,
MUTE, and clocks.
11. During normal operation the user may do the following:
a.
Write to the master or individual-channel volume registers.
b.
Write to the soft-mute register.
c.
Write to the clock and serial data interface format registers (in manual clock mode only).
d.
Write to bit 6 of register 0x05 to enter/exit all-channel shutdown. No other bits of register 0x05 may be
altered. After issuing the all-channel shutdown command, no further I2C transactions that address this
device are allowed for a period of at least: 1 ms + 1.3 × (period specified in start/stop register 0x1A) .
e.
PDN may be asserted (low) at any time. Once PDN is asserted, no I2C transactions that address this
device may be issued until PDN has been deasserted and the part has returned to active mode.
NOTE: When the device is in a powered down state (initiated via PDN), the part is not reset if RESET
is asserted.
NOTE: Once RESET is asserted, and as long as the part is in a reset state, the part does not power
down if PDN is asserted. For powering the part down, a negative edge on PDN must be issued when
RESET is high and the part is not in a reset state.
NOTE: No registers besides those explicitly listed in Steps a.–d. should be altered during normal
operation (i.e., after exiting all-channel shutdown).
NOTE: No registers should be read during normal operation (i.e., after exiting all-channel shutdown) .
12. To reconfigure registers:
a.
Return to all-channel shutdown (observe the shutdown wait time as specified in Step 11.d.).
b.
Drive PDN = 1, and hold MUTE stable.
c.
Provide a stable MCLK, LRCLK, and SCLK.
d.
Repeat configuration starting from step (6).
Table 2. Serial Control Interface Register Summary (1)
NO. OF
INITIALIZATION
SUBADDRESS
REGISTER NAME
CONTENTS
BYTES
VALUE
A u indicates unused bits.
0x00
Clock control register
1
Description shown in subsequent section
0x6C
0x01
Device ID register
1
Description shown in subsequent section
0x2A
0x02
Error status register
1
Description shown in subsequent section
0x00
0x03
System control register 1
1
Description shown in subsequent section
0xA0
0x04
Serial data interface
1
Description shown in subsequent section
0x05
register
0x05
System control register 2
1
Description shown in subsequent section
0x40
0x06
Soft mute register
1
Description shown in subsequent section
0x00
0x07
Master volume
1
Description shown in subsequent section
0xFF (mute)
0x08
Channel 1 vol
1
Description shown in subsequent section
0x30 (0 dB)
0x09
Channel 2 vol
1
Description shown in subsequent section
0x30 (0 dB)
0x0A
Channel 3 vol
1
Description shown in subsequent section
0x30 (0 dB)
0x0B
Channel 4 vol
1
Description shown in subsequent section
0x30 (0 dB)
0x0C
HP volume
1
Description shown in subsequent section
0x30 (0 dB)
0x0D
Channel 6 vol
1
Description shown in subsequent section
0x30 (0 dB)
0x0E
Volume configuration
1
Description shown in subsequent section
0x91
register
0x0F
1
Reserved(2)
0x10
Modulation limit register
1
Description shown in subsequent section
0x02
0x11
IC delay channel 1
1
Description shown in subsequent section
0x4C
(1)
(2)
Reserved registers should not be accessed.
40
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