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參數(shù)資料
| 型號： | TAS5613PHD |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 音頻／視頻放大 |
| 英文描述： | 150 W, 2 CHANNEL, AUDIO AMPLIFIER, PQFP64 |
| 封裝： | GREEN, PLASTIC, HTQFP-64 |
| 文件頁數(shù)： | 11/28頁 |
| 文件大小： | 1505K |
| 代理商： | TAS5613PHD |
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SLAS711A
– JUNE 2010 – REVISED MARCH 2011
there are no shorts from OUT_X to GND_X, the second step tests that there are no shorts from OUT_X to
PVDD_X. The total duration of this process is roughly proportional to the capacitance of the output LC filter. The
typical duration is
< 15ms/μF. While the PPSC detection is in progress, SD is kept low, and the device will not
react to changes applied to the RESET pins. If no shorts are present the PPSC detection passes, and SD is
released. A device reset will not start a new PPSC detection. PPSC detection is enabled in BTL and PBTL output
configurations, the detection is not performed in SE mode. To make sure not to trip the PPSC detection system it
is recommended not to insert resistive load to GND_X or PVDD_X.
OVERTEMPERATURE PROTECTION
PHD Package
The TAS5613A PHD package option has a three-level temperature-protection system that asserts an active-low
warning signal (OTW1) when the device junction temperature exceeds 100
°C (typical), (OTW2) when the device
junction temperature exceeds 125
°C (typical) and, if the device junction temperature exceeds 155°C (typical), the
device is put into thermal shutdown, resulting in all half-bridge outputs being set in the high-impedance (Hi-Z)
state and SD being asserted low. OTE is latched in this case. To clear the OTE latch, RESET must be asserted.
Thereafter, the device resumes normal operation.
UNDERVOLTAGE PROTECTION (UVP) AND POWER-ON RESET (POR)
The UVP and POR circuits of the TAS5613A fully protect the device in any power-up/down and brownout
situation. While powering up, the POR circuit resets the overload circuit (OLP) and ensures that all circuits are
fully operational when the GVDD_X and VDD supply voltages reach stated in the Electrical Characteristics table.
Although GVDD_X and VDD are independently monitored, a supply voltage drop below the UVP threshold on
any VDD or GVDD_X pin results in all half-bridge outputs immediately being set in the high-impedance (Hi-Z)
state and SD being asserted low. The device automatically resumes operation when all supply voltages have
increased above the UVP threshold.
DEVICE RESET
When RESET is asserted low, all power-stage FETs in the four half-bridges are forced into a high-impedance
(Hi-Z) state.
In BTL modes, to accommodate bootstrap charging prior to switching start, asserting the reset input low enables
weak pulldown of the half-bridge outputs. In the SE mode, the output is forced into a high impedance state when
asserting the reset input low.
Asserting reset input low removes any fault information to be signalled on the SD output, i.e., SD is forced high.
A rising-edge transition on reset input allows the device to resume operation after an overload fault. To ensure
thermal reliability, the rising edge of reset must occur no sooner than 4 ms after the falling edge of SD.
SYSTEM DESIGN CONSIDERATION
A rising-edge transition on reset input allows the device to execute the startup sequence and starts switching.
Apply only audio when the state of READY is high that will start and stop the amplifier without having audible
artifacts that is heard in the output transducers.
The CLIP signal is indicating that the output is approaching clipping. The signal can be used to either an audio
volume decrease or intelligent power supply controlling a low and a high rail.
The device is inverting the audio signal from input to output.
The VREG pin is not recommended to be used as a voltage source for external circuitry.
OSCILLATOR
The oscillator frequency can be trimmed by external control of the FREQ_ADJ pin.
To reduce interference problems while using radio receiver tuned within the AM band, the switching frequency
can be changed from nominal to lower values. These values should be chosen such that the nominal and the
lower value switching frequencies together results in the fewest cases of interference throughout the AM band.
can be selected by the value of the FREQ_ADJ resistor connected to AGND in master mode.
Copyright
2010–2011, Texas Instruments Incorporated
19
Product Folder Link(s): TAS5613A
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TAS5613PHD | 制造商:Texas Instruments 功能描述:Speaker Amplifier IC |
| TAS5613PHD2EVM | 功能描述:音頻 IC 開發(fā)工具 TAS5613PHD Eval Mod RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Kits 類型:Audio Amplifiers 工具用于評估:TAS5614L 工作電源電壓:12 V to 38 V |
| TAS5613PHD2EVM | 制造商:Texas Instruments 功能描述:DEVELOPMENT TOOL 制造商:Texas Instruments 功能描述:TAS5613PHD, AUDIO POWER AMP, CLASS D, EVAL MODULE |
| TAS5613PHDR | 功能描述:音頻放大器 150W Stereo PurePath HD Ana-In Pwr Stage RoHS:否 制造商:STMicroelectronics 產(chǎn)品:General Purpose Audio Amplifiers 輸出類型:Digital 輸出功率: THD + 噪聲: 工作電源電壓:3.3 V 電源電流: 最大功率耗散: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TQFP-64 封裝:Reel |
| TAS5614 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:150W STEREO / 300W MONO PurePath? HD DIGITAL-INPUT POWER STAGE |
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