參數(shù)資料
型號(hào): TAS5508PAGRG4
廠商: TEXAS INSTRUMENTS INC
元件分類: 消費(fèi)家電
英文描述: SPECIALTY CONSUMER CIRCUIT, PQFP64
封裝: GREEN, PLASTIC, TQFP-64
文件頁(yè)數(shù): 79/105頁(yè)
文件大?。?/td> 1286K
代理商: TAS5508PAGRG4
7.7
Headphone Configuration Control Register (0x0D)
7.8
Serial Data Interface Control Register (0x0E)
TAS5508
8-Channel Digital Audio PWM Processor
www.ti.com
SLES091D – FEBRUARY 2004 – REVISED JULY 2009
Table 7-6. Channel Configuration Control Register Format
D7
D6
D5
D4
D3
D2
D1
D0
FUNCTION
0
Disable back-end reset sequence for a channel – BEErrorRecEn
1
Enable back-end reset sequence for a channel
0
Valid does not have to be low for this channel to be reset BEValidRst
1
Valid must be low for this channel to be reset
0
Valid does not have to be low for this channel to be muted BEValidMute
1
Valid must be low for this channel to be muted
0
Normal BEPolarity
1
Switches PWM+ and PWM– and inverts audio signal
0
Do not remap output to comply with 5182 interface
1
Remap output to comply with 5182 interface
0
Do not go to low-low in mute – BELowMute
1
Go to low-low in mute
0
Do not remap Hi-Z state to low-low state – BE5111BsMute
1
Remap Hi-Z state to low-low state
Bit D0 is Don't Care.
Table 7-7. Headphone Configuration Control Register Format
D7
D6
D5
D4
D3
D2
D1
D0
FUNCTION
0
Disable back-end reset sequence for a channel – BEErrorRecEn
1
Enable back-end reset sequence for a channel
0
Valid does not have to be low for this channel to be reset
BEValidRst
1
Valid must be low for this channel to be reset
0
Valid does not have to be low for this channel to be muted
BEValidMute
1
Valid must be low for this channel to be muted
0
Normal BEPolarity
1
Switches PWM+ and PWM– and inverts audio signal
0
Do not remap output to comply with 5182 interface
1
Remap output to comply with 5182 interface
0
Do not go to low-low in mute – BELowMute
1
Go to low-low in mute
0
Do not remap Hi-Z state to low-low state – BE5111BsMute
1
Remap Hi-Z state to low-low state
Nine serial modes can be programmed via the I2C interface.
Table 7-8. Serial Data Interface Control Register Format
RECEIVE SERIAL DATA
WORD LENGTHS
D7–D4
D3
D2
D1
D0
INTERFACE FORMAT
Right-justified
16
0000
0
Right-justified
20
0000
0
1
Right-justified
24
0000
0
1
0
I2S
16
0000
0
1
Serial-Control Interface Register Definitions
75
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