參數(shù)資料
型號(hào)： TAS5508BPAGR
廠商： TEXAS INSTRUMENTS INC
元件分類： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQFP64
封裝： GREEN, PLASTIC, TQFP-64
文件頁數(shù)： 53/103頁
文件大?。?/td> 1198K
代理商： TAS5508BPAGR
4.5
Electrical Characteristics
4.6
PWM Operation
4.7
Switching Characteristics
4.7.1
Clock Signals
TAS5508B
8-Channel Digital Audio PWM Processor
www.ti.com
SLES162C – DECEMBER 2005 – REVISED JULY 2009
Over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
3.3-V TTL and 5-V(1) tolerant
IOH = –4 mA
2.4
VOH
High-level output voltage
V
1.8-V LVCMOS (XTL_OUT)
IOH = –0.55 mA
1.44
3.3-V TTL and 5-V(1) tolerant
IOL = 4 mA
0.5
VOL
Low-level output voltage
V
1.8-V LVCMOS (XTL_OUT)
IOL = 0.75 mA
0.5
IOZ
High-impedance output current
3.3-V TTL
±20
A
3.3-V TTL
VI = VIL
±1
IIL
Low-level input current
1.8-V LVCMOS (XTL_IN)
VI = VIL
±1
A
5-V tolerant(2)
VI = 0 V, DVDD = 3 V
±1
3.3-V TTL
VI = VIH
±1
IIH
High-level input current
1.8-V LVCMOS (XTL_IN)
VI = VIH
±1
A
5-V tolerant(2)
VI = 5.5 V, DVDD = 3 V
±20
fS = 48 kHz
140
fS = 96 kHz
150
Digital supply voltage, DVDD
fS = 192 kHz
155
IDD
Input supply current
mA
Power down
8
Normal
20
Analog supply voltage, AVDD
Power down
2
(1)
5-V tolerant outputs are SCL and SDA.
(2)
5-V tolerant inputs are RESET, PDN, MUTE, HP_SEL, SCLK, LRCLK, MCLK, SDIN1, SDIN2, SDIN3, SDIN4, SDA, and SCL.
Over recommended operating conditions
PARAMETER
TEST CONDITIONS
MODE
VALUE
UNIT
32-kHz data rate
±2%
12
× sample rate
384
kHz
Output sample rate 1
×–8× oversampled
44.1-, 88.2-, 176.4-kHz data rate
±2%
8
×, 4×, or 2× sample rate
352.8
kHz
48-, 96-, 192-kHz data rate
±1%
8
×, 4×, or 2× sample rate
384
kHz
PLL input parameters and external filter components over recommended operating conditions (unless otherwise noted)
(1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
fXTALI
Frequency, XTAL IN
Only use 13.5-MHz crystal
≤1000 ppm
13.5
MHz
fMCLKI
Frequency, MCLK (1/tcyc2)
2
50
MHz
MCLK duty cycle
40%
50%
60%
≥2-V MCLK = 49.152 MHz, within the min
MCLK minimum high time
5
ns
and max duty cycle constraints
≤0.8-V MCLK = 49.152 MHz, within the min
MCLK minimum low time
5
ns
and max duty cycle constraints
LRCLK allowable drift before LRCLK reset
–10
10
MCLKs
External PLL filter capacitors C11 and C12
SMD 0603 Y5V
100
nF
External PLL filter capacitors C10 and C13
SMD 0603 Y5V
10
nF
External PLL filter resistors R10 and R11
SMD 0603, metal film
200
External VRA_PLL decoupling C14
SMD, Y5V
100
nF
(1)
See the TAS5508B Example Application Schematic, Section 8.
Electrical Specifications
53
相關(guān)PDF資料
PDF描述
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