參數(shù)資料
型號: TAS5508BPAGG4
廠商: TEXAS INSTRUMENTS INC
元件分類: 消費家電
英文描述: SPECIALTY CONSUMER CIRCUIT, PQFP64
封裝: GREEN, PLASTIC, TQFP-64
文件頁數(shù): 88/103頁
文件大?。?/td> 1198K
代理商: TAS5508BPAGG4
7.19 DRC2 Control Register, Channel 8 (0x97)
7.20 DRC1 Data Registers (0x98–0x9C)
TAS5508B
8-Channel Digital Audio PWM Processor
www.ti.com
SLES162C – DECEMBER 2005 – REVISED JULY 2009
Note that there must be a 10-ms delay between a write to register 0x96 and a write to register 0x97.
Table 7-20. Channel-8 DRC2 Control Register Format
D31–D2
D1
D0
FUNCTION
0
Channel 8 (node r): no DRC
0
1
Channel 8 (node r): pre-volume DRC
0
1
0
Channel 8 (node r): post-volume DRC
0
1
Channel 8 (node r): no DRC
DRC1 applies to channels 1, 2, 3, 4, 5, 6, and 7.
Table 7-21. DRC1 Data Register Format
I2C
TOTAL
REGISTER NAME
DESCRIPTION OF CONTENTS
DEFAULT STATE
SUB-
BYTES
ADDRESS
Channel 1, 2, 3, 4, 5, 6, and 7 DRC1
u[31:28], E[27:24], E[23:16], E[15:8], E[7:0]
0x00, 0x00, 0x88, 0x3F
energy
0x98
8
Channel 1, 2, 3, 4, 5, 6, and 7 DRC1
u[31:28], 1–E[27:24], 1–E[23:16], 1–E[15:8], 1–E[7:0]
0x00, 0x7F, 0x77, 0xC0
(1 – energy)
Channel 1, 2, 3, 4, 5, 6, and 7 DRC1
u[31:24], u[23:16], T1[15:8], T1[7:0]
0x00, 0x00, 0x00, 0x00
threshold upper 16 bits (T1)
Channel 1, 2, 3, 4, 5, 6, and 7 DRC1
T1[31:24], T1[23:16], T1[15:8], T1[7:0]
0x0B, 0x20, 0xE2, 0xB2
threshold lower 32 bits (T1)
0x99
16
Channel 1, 2, 3, 4, 5, 6, and 7 DRC1
u[31:24], u[23:16], T2[15:8], T2[7:0]
0x00, 0x00, 0x00, 0x00
threshold upper 16 bits (T2)
Channel 1, 2, 3, 4, 5, 6, and 7 DRC1
T2[31:24], T2[23:16], T2[15:8], T2[7:0]
0x06, 0xF9, 0xDE, 0x58
threshold lower 32 bits (T2)
Channel 1, 2, 3, 4, 5, 6, and 7 DRC1
u[31:28], k0[27:24], k0[23:16], k0[15:8], k0[7:0]
0x00, 0x40, 0x00, 0x00
slope (k0)
Channel 1, 2, 3, 4, 5, 6, and 7 DRC1
u[31:28], k1[27:24], k1[23:16], k1[15:8], k1[7:0]
0x0F, 0xC0, 0x00, 0x00
0x9A
12
slope (k1)
Channel 1, 2, 3, 4, 5, 6, and 7 DRC1
u[31:28], k2[27:24], k2[23:16], k2[15:8], k2[7:0]
0x0F, 0x90, 0x00, 0x00
slope (k2)
Channel 1, 2, 3, 4, 5, 6, and 7 DRC1
u[31:24], u[23:16], O1[15:8], O1[7:0]
0x00, 0x00, 0xFF, 0xFF
offset-1 upper 16 bits (O1)
Channel 1, 2, 3, 4, 5, 6, and 7 DRC1
O1[31:24], O1[23:16], O1[15:8], O1[7:0]
0xFF, 0x82, 0x30, 0x98
offset-1 lower 32 bits (O1)
0x9B
16
Channel 1, 2, 3, 4, 5, 6, and 7 DRC1
u[31:24], u[23:16], O2[15:8], O2[7:0]
0x00, 0x00, 0x00, 0x00
offset-2 upper 16 bits (O2)
Channel 1, 2, 3, 4, 5, 6, and 7 DRC1
O2[31:24], O2[23:16], O2[15:8], O2[7:0]
0x01, 0x95, 0xB2, 0xC0
offset-2 lower 32 bits (O2)
Channel 1, 2, 3, 4, 5, 6, and 7 DRC1
u[31:28], A[27:24], A[23:16], A[15:8], A[7:0]
0x00, 0x00, 0x88, 0x3F
attack
Channel 1, 2, 3, 4, 5, 6, and 7 DRC1
u[31:28], 1–A[27:24], 1–A[23:16], 1–A[15:8], 1–A[7:0]
0x00, 0x7F, 0x77, 0xC0
(1 – attack)
0x9C
16
Channel 1, 2, 3, 4, 5, 6, and 7 DRC1
u[31:28], D[27:24], D[23:16], D[15:8], D[7:0]
0x00, 0x00, 0x00, 0x56
decay
Channel 1, 2, 3, 4, 5, 6, and 7 DRC1
u[31:28], 1–D[27:24], 1–D[23:16], 1–D[15:8], 1–D[7:0]
0x00, 0x3F, 0xFF, 0xA8
(1 – decay)
Serial-Control Interface Register Definitions
85
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