參數(shù)資料
型號: TAS5342ADDV
廠商: TEXAS INSTRUMENTS INC
元件分類: 音頻/視頻放大
英文描述: 100 W, 2 CHANNEL, AUDIO AMPLIFIER, PDSO44
封裝: GREEN, PLASTIC, HTSSOP-44
文件頁數(shù): 26/27頁
文件大?。?/td> 835K
代理商: TAS5342ADDV
RECOMMENDED OPERATING CONDITIONS
AUDIO SPECIFICATIONS (BTL)
SLAS623 – NOVEMBER 2008 ........................................................................................................................................................................................... www.ti.com
MIN
TYP
MAX
UNIT
PVDD_X
Half-bridge supply voltage
0
31.5
34
V
Supply voltage for logic regulators and
GVDD_X
10.8
12
13.2
V
gate-drive circuitry
VDD
Digital regulator supply voltage
10.8
12
13.2
V
RL (BTL)
3
4
Resistive load impedance (no Cycle-by_Cycle
RL (SE)
current control), recommended demodulation
2.25
3
filter
RL (PBTL)
1.5
2
LOutput (BTL)
5
10
Minimum output inductance under
LOutput (SE)
Output-filter inductance
5
10
H
short-circuit condition
LOutput (PBTL)
5
10
fS
PWM frame rate
192
384
432
kHz
tLOW
Minimum low-state pulse duration per PWM
30
nS
Frame, noise shaper enabled
CPVDD
PVDD close decoupling capacitors
0.1
F
CBST
Bootstrap capacitor, selected value supports
33
nF
PWM frame rates from 192 kHz to 432 kHz
ROC
Over-current programming resistor
Resistor tolerance = 5%
27
47
k
REXT-PULLUP
External pull-up resistor to +3.3V to +5.0V for
3.3
4.7
k
SD or OTW
TJ
Junction temperature
0
125
°C
Audio performance is recorded as a chipset consisting of a TAS5518 pwm processor (modulation index limited to 97.7%) and
a TAS5342A power stage. PCB and system configuraton are in accordance with recommended guidelines. Audio frequency =
1 kHz, PVDD_x = 31.5 V, GVDD_x = 12 V, RL = 4 , fS = 384 kHz, ROC = 27 k, TC = 75°C, Output Filter: LDEM = 10 H,
CDEM = 470 nF, unless otherwise noted.
TAS5342A
PARAMETER
TEST CONDITIONS
UNIT
MIN
TYP
MAX
RL = 4 , 10% THD+N, clipped input signal
100
POMAX
Maximum Power Output
RL = 6 , 10% THD+N, clipped input signal
80
RL = 8 , 10% THD+N, clipped input signal
65
W
RL = 4 , 0 dBFS, unclipped input signal
80
PO
Unclipped Power Output
RL = 6 , 0 dBFS, unclipped input signal
64
RL = 8 , 0 dBFS, unclipped input signal
50
0 dBFS; AES17 filter
0.4%
THD+N
Total harmonic distortion + noise
1 W; AES17 filter
0.09%
Vn
Output integrated noise
A-weighted, AES17 filter, Auto mute disabled
45
V
SNR
Signal-to-noise ratio (1)
A-weighted, AES17 filter, Auto mute disabled
110
dB
A-weighted, input level = –60 dBFS, AES17
DNR
Dynamic range
110
dB
filter
DC Offset
Output offset voltage
±15
mV
Pidle
Power dissipation due to idle losses
PO = 0 W, all halfbridges switching
(2)
2
W
(IPVDD_X)
(1)
SNR is calculated relative to 0-dBFS input level.
(2)
Actual system idle losses are affected by core losses of output inductors.
8
Copyright 2008, Texas Instruments Incorporated
Product Folder Link(s): TAS5342A
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