
Are
Clocks
Stable?
No
Yes
RESET Pin = Low
Enable Mute and
Wait for Completion
Change fMCLK
RESET Pin = High
After
TAS3204
Initializes,
Re-initialize
I C Registers
2
SLES197C – APRIL 2007 – REVISED MARCH 2011
www.ti.com
Figure 3-2. Master Clock Frequency (fMCLK) Change Procedure
Table 3-1. TAS3204 MCLK and LRCLK Common Values (MCLK = 24.576 MHz or MCLK = 22.579 MHz)
MCLK/
MCLK
SCLKIN
SCLK_IN
SCLK_OUT
FS Sample
Ch Per
LRCLK
Ch Per
LRCLK
PLL
FDSPCLK
Freq
Rate
Freq
Rate
fDSPCLK/fS
Rate (kHz)
SDIN
Ratio
SDOUT
(FS)
Multiplier
(MHz)
(× fS)
(MHz)
(× fS)
Slave Mode, 2 Channels In, 2 Channels Out
44.1
2
512
22.579
64
2.822
64
2
64
5.5
124.2
2816
48
2
256
24.576
64
3.072
64
2
64
5.5
135.2
2816
Master Mode, 2 Channels In, 2 Channels Out
48
2
256
24.576
N/A
64
2
64
5.5
135.2
2816
10
TAS3204 Clocking System
Copyright 2007–2011, Texas Instruments Incorporated