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| 型號(hào)： | TAS3103IDBT |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類(lèi)： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PDSO38 |
| 封裝： | GREEN, PLASTIC, TSSOP-38 |
| 文件頁(yè)數(shù)： | 85/148頁(yè) |
| 文件大?。?/td> | 1247K |
| 代理商： | TAS3103IDBT |
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210
U1
ORIN
TAS3103
SDOUT1
U2
ORIN
TAS3103
SDOUT1
(AB = ’1’)
(AB = ’0’)
LR
UU2
LRCLK
SDOUT1U1
32
LR
U
LRCLK
U2
V
W
X
32
U1
U
V
W
0
X
32
UU1
VU2
WU2
XU2
VU1
WU1
XU1
Figure 210. 8 CH TDM Format Using SAP Modes 0101 and 1000
U1
ORIN
TAS3103
SDOUT1
U2
ORIN
TAS3103
SDOUT1
(AB = 0)
(AB = 1)
LR
UU1
LRCLK
SDOUT1U1
32
LR
U
LRCLK
U1
V
W
0
32
U2
U
0
W
Y
0
32
UU2
VU1
WU1
YU2
WU2
Figure 211. 6 CH Data, 8 CH Transfer TDM Format Using SAP Modes 0101 and 1000
For these same two modes, if register X in chip AB = 0 is set to zero, and registers V and X in chip AB = 1 are set
to zero, the resulting format is a 6 CH data, 8 CH transfer format. This option is shown in Figure 211.
The data output format in Figure 211 is identical to that realized using data output formats 1100 and 1110 in
Figure 27. The difference is that SAP modes 1010 and 1000 provide six independent monaural channels to process
the data, whereas SAP modes 1100 and 1110 provide only three independent monaural channels to process the data.
2.1.2
Processing Flow—SAP Input to SAP Output
All SAP data format options other than I2S result in a two-sample delay from input to output, as illustrated in
Figure 212. Figure 212 is also relevant if I2S formatting is used for both the input SAP and the output SAP (the
polarity of LRCLK in Figure 212 has to be inverted in this case). However, if I2S format conversions are performed
between input and output, the delay becomes either 1.5 samples or 2.5 samples, depending on the processing clock
frequency selected for the digital audio processor (DAP) relative to the sample rate of the incoming data. The input
to output delay for an I2S input format and a non-I2S output format is illustrated in Figure 213(a), and Figure 213(b)
illustrates the delay for a non-I2S input format and an I2S output format. In each case, two distinct input to output delay
times are shown: a 1.5 sample delay time if the processing time in the DAP is less than half the sample period, and
a 2.5 sample delay time if the processing time in the DAP is greater than half the sample period.
The departure from the two-sample input to output processing delay when I2S format conversions are performed is
due to the use of a common LRCLK. The I2S format uses the falling edge of LRCLK to begin a sample period, whereas
all other formats use the rising edge of LRCLK to begin a sample period. This means that the input SAP and digital
audio processor (DAP) operate on sample windows that are 180
° out of phase with respect to the sample window
used by the output SAP. This phase difference results in the output SAP outputting a new data sample at the midpoint
of the sample period used by the DAP to process the data. If the processing cycle completes all processing tasks
before the midpoint of the processing sample period, the output SAP outputs this processed data. However, if the
processing time extends past the midpoint of the processing sample period, the output SAP outputs the data
processed during the previous processing sample period. In the former case, the delay from input to output is 1.5
samples. In the latter case, the delay from input to output is 2.5 samples.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| TAS3103IDBTR | 功能描述:音頻 DSP Digital Audio Processor RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
| TAS3103IDBTRG4 | 功能描述:音頻 DSP Digital Audio Processor RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
| TAS3108 | 制造商:TI 制造商全稱(chēng):Texas Instruments 功能描述:AUDIO DIGITAL SIGNAL PROCESSORS |
| TAS3108DCP | 功能描述:音頻 DSP 8-Channel Audio DSP RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
| TAS3108DCPG4 | 功能描述:音頻 DSP 8-Channel Audio DSP RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
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