參數(shù)資料
型號： TA1360AFG
廠商： Toshiba Corporation
英文描述： YCbCr/YPbPr Signal and Sync Processor for Digital TV, Progressive Scan TV and Double Scan TV
中文描述： YCbCr /色差信號處理器和同步數(shù)字電視，逐行掃描電視和雙掃描電視
文件頁數(shù)： 14/110頁
文件大?。?/td> 1425K
代理商： TA1360AFG
TA1360AFG
2003-01-21
14
Bus Control Features
Write Mode
Resister Name
Description
Preset Value
H-FREQ1/2
Switches horizontal oscillation frequency. (See the appendix 1)
33.75 kHz
H-DUTY
Switches horizontal output duty.
0: 41% 1: 47%
41%
YUV-SW
Switches YUV input.
0: INPUT-1 (Y1/C
b1
/C
r1
) 1: INPUT-2 (Y2/C
b2
/C
r2
)
INPUT-1
DAC 1
Switches DAC controlling output.
0: OPEN (high) 1: ON (low)
Controls 1-bit DAC of open-collector when TEST is 00.
Outputs H/C-SYNC from pin 34 when TEST is 01.
OPEN
DAC 2
Switches DAC controlling output.
0: ON (low), 1: OPEN (high)
Controls 1-bit DAC of open-collector when TEST is 00.
Outputs ACB reference pulse from pin 23 when TEST is 01.
ON
SYNC-SW
Switches sync input.
0: Selects HD/VD input. 1: Selects SYNC input.
HD/VD
HORIZONTAL POSITION
Adjusts horizontal picture position (phase).
0000000:
12.5% 1111111:
+
12.5%
Note: VP output width (pin 35) varies with a change of horizontal position.
CENTER
CLP-PHS
Switches clamp pulse phase.
0: 0.7-
μ
s (2.5%) width, 1.1-
μ
s (3.8%) delay from HD stop phase.
1: 0.7-
μ
s (2.4%) width, 0.2-
μ
s (0.7%) delay from HD stop phase
when no signal, 0.8-
μ
s (2.7%) width that is 1.2-
μ
s (4.2%) delay from FBP start
phase.
Also switches CP phase of CP-OUT (pin 47).
1.1-
μ
s delay
ACB MODE
Sets ACB mode; Sets converged reference level.
00: ACB OFF (cutoff BUS control), 01: ACB ON (5 IRE),
10: ACB ON (10 IRE) 11: ACB ON (20 IRE)
ACB ON
(10 IRE)
SCP-SW
SCP (sand castle pulse) Switches modes.
0: Internal Mode 1: External input Mode
Internal Mode
HBP-PHS1/2
Switches phase of black-stretch-detection stop pulse.
HBP-PHS1
=
0 and HBP-PHS2
=
0: FBP
±
3%
HBP-PHS1
=
0 and HBP-PHS2
=
1: FBP
±
8%
HBP-PHS1
=
1 and HBP-PHS2
=
0: FBP
±
13%
HBP-PHS1
=
1 and HBP-PHS2
=
1: FBP
±
18%
Leaving Y open and setting the test circuit SW2 to C enable to monitor H/V-BPP
(black-stretch-detection stop pulse) width through pin 70.
±
3%
SYNC SEP-LEVEL
Switches Sync SEP-level.
00: 16% 01: 24% 10: 32% 11: 40% (At 1125I/60)
16%
TEST
Test Mode:
Controls 1-bit DAC of open-collector when TEST is 00.
Outputs H/C-SYNC from pin 34, and ACB reference pulse from pin 23 when TEST
is 01.
Do not set TEST to 10/11 for that is shipment TEST Mode.
00
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