參數(shù)資料
型號(hào)： TA1318AFG
廠商： Toshiba Corporation
英文描述： Zener Diode; Application: Low noise; Pd (mW): 250; Vz (V): 4.0 to 4.4; Condition Iz at Vz (mA): 0.5; C (pF) max: -; Condition VR at C (V):   ESD (kV) min: -; Package: DO-35
中文描述： 同步處理器，頻率計(jì)數(shù)器集成電路電視分量信號(hào)
文件頁(yè)數(shù)： 13/42頁(yè)
文件大?。?/td> 370K
代理商： TA1318AFG
TA1318AFG
2006-02-27
13
Bus Control Map
Write Mode
Slave Address: D8/DA/DC
H
Preset
MSB
Sub-Add
D7
MSB
D6
D5
D4
D3
D2
D1
D0
LSB
LSB
00
H-FREQUENCY
HD1/VD1-OUT SW
HD2/VD2-OUT SW
SEPA LEVEL
1000
0000
01
DAC1
DAC2
DAC3
TEST
HD1-INV
HD2-INV
1000
0000
02
V-FREQUENCY
CLP-PHS
FREQ DET SW
INPUT SW
1000
0000
03
HD PHASE
VD1-INV
VD2-INV
1000
0000
Read Mode
Slave Address: D9/DB/DD
H
D7
MSB
D6
D5
D4
D3
D2
D1
D0
LSB
0
POR
V FREQUENCY DET
1
HD-IN
H FREQUENCY DET
Bus Control Functions
Write Mode
(
*
: Preset)
H-FREQUENCY (Horizontal oscillation frequency)
Switches horizontal frequency.
(00): 15.75 kHz
Note: To prevent a horizontal mislock, set (10) 33.75 kHz mode just before (01) 31.5 kHz mode setting when
the horizontal frequency mode is switched to (01) 31.5 kHz mode.(wait time: 1 ms or more)
Additionally, in 31.5 kHz mode, set (10) 33.75 kHz mode at first and set (01) 31.5 kHz mode again,
when 525 p/625 p signal is pulled-in again from no-input.
HD1/VD1-OUT SW (HD1/VD1 output switch)
Switches output from pin 16/28. When set to 00, 01, or 10, outputs HD/VD without synchronization.
When set to 11, outputs HD/VD from the sync circuit. (Note) Synchronized VD width will change, when
HD PHASE will be changed.
*
(00): HD1/VD1
(01): HD2/VD2
(10): HD3/VD3
HD2/VD2-OUT SW (HD2/VD2 output switch)
Switches output from pin 19/29. When set to 00, 01, or 10, outputs HD/VD without synchronization.
When set to 11, outputs HD/VD from the sync circuit. (Note) Synchronized VD width will change, when
HD PHASE will be changed.
*
(00): HD1/VD1
(01): HD2/VD2
(10): HD3/VD3
SEPA LEVEL (Sync separation level switch)
Switches sync separation level of pin 24/26. Set values are the levels from sync tip. Sync separation level
is changed according to the ratio of H-SYNC width during 1H period.
*
(00): 10IRE
(01): 15IRE
(10): 20IRE
DAC1 (DAC1 control)
Controls 2-bit DAC (pin 12).
(00): 1 V
(01): 3 V
*
(10): 5 V
DAC2 (DAC2 control)
Controls 2-bit DAC (pin 25).
*
(00): 1 V
(01): 3 V
(10): 5 V
DAC3 (DAC3 control)
Controls open collector 1-bit DAC (pin 30).
*
(0): OPEN (HIGH)
(1): ON (LOW)
(01): 31.5 kHz
*
(10): 33.75 kHz
(11): 45 kHz
(11): Synchronized HD/VD
(11): Synchronized HD/VD
(11): 25IRE (at 1125I/60)
(11): 7 V
(11): 7 V
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