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參數(shù)資料
| 型號： | TA1296FN |
| 廠商： | Toshiba Corporation |
| 英文描述： | Down-Converter IC with PLL for Satellite Tuner |
| 中文描述： | 向下轉換器與鎖相環(huán)衛(wèi)星調(diào)諧器集成電路 |
| 文件頁數(shù)： | 10/22頁 |
| 文件大小： | 227K |
| 代理商： | TA1296FN |
TA1296FN
2002-02-12
10
Bus Line Characteristics
Parameter
Symbol
Test
Circuit
Test Condition
Min
Typ.
Max
Unit
SCL clock frequency
fSCL
0
100
kHz
Bus free time between a STOP and
START conditions
t
BUF
4.7
s
Hold time for repeated START
condition
SCL clock low period
SCL clock high period
t
HD
; STA
4
s
t
LOW
t
HIGH
4.7
4
s
s
Set-up time for repeated START
condition
Data hold time
Data set-up time
Rise time for SDA and SCL signals
f
SU
; STA
4.7
s
t
HD
; DAT
t
SU
; DAT
tR
0
s
250
ns
ns
1000
Fall time for SDA and SCL signals
tF
300
ns
Set-up time for STOP condition
tsU; STO
Please refer to data timing
chart.
4
s
t
HD
; STA
tSU; STO
SDA
SCL
t
BUF
t
LOW
tR
tF
t
HD
; STA
t
HD
; DAT
t
HIGH
t
SU
; DAT
t
SU
; STA
P
S
Sr
P
Figure 1 I
2
C Bus Data Timing Chart (rising-edge timing)
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