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| 型號(hào)： | T9000 |
| 英文描述： | ISDN Network Termination Node (NTN) Device |
| 中文描述： | ISDN網(wǎng)絡(luò)終端節(jié)點(diǎn)（新界北）設(shè)備 |
| 文件頁(yè)數(shù)： | 17/126頁(yè) |
| 文件大?。?/td> | 2127K |
| 代理商： | T9000 |
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Lucent Technologies Inc.
17
Preliminary Data Sheet
November 2000
ISDN Network Termination Node (NTN) Device
T9000
6 Functional Modules
This section covers the functionality of the NTN core
modules.
6.1 80C32 Microcontroller Module (80C32
Block)
The NTN IC includes an embedded 80C32 microcon-
troller, incorporating a 256-byte internal RAM, three
16-bit timer/counters, six interrupt sources, and one
serial port I/O.
Typical functions of the microcontroller module are as
follows:
I
Definition of operation modes for all other NTN mod-
ules (U-interface, S/T-interface, etc.)
I
Configuration of the 2B+D data flow paths in the
DFAC module
I
Layer 2 and layer 3 processing of the D channel for
POTS calls
I
Supervision of the POTS circuitry
I
Device power management
6.2 Program Address Space
The on-chip 64K x 8 mask-programmable ROM occu-
pies the full program memory space addressable by
the 80C32. The 80C32 addresses this memory via the
microcontroller interface (UCI) module.
The internal ROM can be disabled so that code from an
external ROM can be executed by tying the EA pin low.
The microcontroller then fetches the program instruc-
tions through its external access port (see Table 5).
Applications requiring a larger program space than the
64K x 8 available with the standard 80C32 may use
GPIO ports to extend the address space using a pag-
ing scheme.
6.3 Data Address Space
The NTN data address space is comprised of several
distinct regions as shown in Figure 3.
The 80C32 internal RAM is an integral part of the
80C32 architecture and is accessed using the 80C32
MOV instruction (see any standard 80C32 data sheet
for details on the internal memory space).
The NTN has on-chip registers and SRAM that occupy
the lowest 4 Kbytes of the 80C32’s external data mem-
ory address space and is accessed using the 80C32
MOVX instruction. The on-chip read and write signals
from the 80C32 (shown in Figure 3 as RDi and WRi)
are asserted during access to this memory space.
The lowest 94 bytes of the 80C32 external space
(00—5Dh) are comprised of the device configuration
and control registers, and the remaining (4002) bytes
(5Eh—0FFFh) are comprised of SRAM.
The NTN can also access off-chip RAM up to the 64K
address space limit through the external access port
(see Table 5). When accessing the 4K on-chip RAM at
the bottom of the address space, the on-chip external
qualifier function shown in Figure 3 prevents the RDi
and WRi signals from propagating to the NTN pins RD
and WR (the pins remain 3-stated). When accessing
an address outside the 4K range of the on-chip mem-
ory space, the RD and WR signals appear on the NTN
pins RD and WR. The external qualifier function elimi-
nates the need for any external decoding (chip-select)
logic when an external RAM is being used. In this
scheme, the lowest 4K of any external RAM is not
usable. External address decoding logic may be used if
it is desirable to use the lowest 4K of the external RAM.
6.4 Timers
Timer 0 and timer 1 can be configured as either inde-
pendent timers or counters as specified in the 80C32
data sheet. In counter mode, GPIO ports 1.5 and 1.6
may be configured to generate timer 0’s and timer 1’s
trigger sources, respectively (see Section 11, GPIO
Ports). Timer 2 can be configured as a timer, a counter,
or as a serial baud rate generator. In counter and baud
generator mode, GPIO 1.7 may be configured as timer
2’s trigger source.
6.5 Interrupts
The 80C32 accepts six interrupts sources. These inter-
rupt sources are interrupt lines INT0 and INT1 (the
80C32 block external interrupts); timer 0, timer 1, and
timer 2; and a serial port interrupt.
The NTN has an embedded interrupt controller which
collapses a large number of interrupt sources (GPIR,
UIR, SIR, PWIR, CMIR, GCIR, and HIR) into the two
80C32 interrupt inputs INT0 and INT1. Since the inter-
rupt controller can be viewed as an AND function of the
NTN interrupt sources, the 80C32 interrupts should be
programmed as level-triggered interrupts (TCON.IT0
and TCON.IT1, cleared to 0, the reset default condi-
tion).
If external edge-triggered interrupts sources must be
interfaces to the NTN, ports GPIO0[3:0] and
GPIO1[3:0] can be used.
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