參數(shù)資料
型號： T89C51RD2-SMWI-L
廠商： Atmel Corp.
英文描述： 0 to 40MHz Flash Programmable 8-bit Microcontroller
中文描述： 0至40MHz可編程閃存8位微控制器
文件頁數(shù)： 21/170頁
文件大?。?/td> 1927K
代理商： T89C51RD2-SMWI-L
21
A/T89C51CC01
4129L–CAN–08/05
Power Management
Two power reduction modes are implemented in the T89C51CC01: the Idle mode and
the Power-down mode. These modes are detailed in the following sections. In addition
to these power reduction modes, the clocks of the core and peripherals can be dynami-
cally divided by 2 using the X2 Mode detailed in Section “Clock”.
Reset Pin
In order to start-up (cold reset) or to restart (warm reset) properly the microcontroller, a
high level has to be applied on the RST pin. A bad level leads to a wrong initialisation of
the internal registers like SFRs, PC, etc. and to unpredictable behavior of the microcon-
troller. A warm reset can be applied either directly on the RST pin or indirectly by an
internal reset source such as a watchdog, PCA, timer, etc.
At Power-up (Cold Reset)
Two conditions are required before enabling a CPU start-up:
VDD must reach the specified VDD range,
The level on xtal1 input must be outside the specification (VIH, VIL).
If one of these two conditions are not met, the microcontroller does not start correctly
and can execute an instruction fetch from anywhere in the program space. An active
level applied on the RST pin must be maintained until both of the above conditions are
met. A reset is active when the level VIH1 is reached and when the pulse width covers
the period of time where VDD and the oscillator are not stabilized. Two parameters have
to be taken into account to determine the reset pulse width:
VDD rise time (vddrst),
Oscillator startup time (oscrst).
To determine the capacitor the highest value of these two parameters has to be chosen.
The reset circuitry is shown in Figure 7.
Figure 7.
Reset Circuitry
Table 14 and Table 15 give some typical examples for three values of VDD rise times,
two values of oscillator start-up time and two pull-down resistor values.
Table 14.
Minimum Reset Capacitor for a 15k Pull-down Resistor
Note:
These values assume VDD starts from 0v to the nominal value. If the time between two
on/off sequences is too fast, the power-supply de coupling capacitors may not be fully
discharged, leading to a bad reset sequence.
oscrst/vddrst
1ms
10ms
100ms
5ms
2.7μF
4.7μF
47μF
20ms
10μF
15μF
47μF
0
VDD
Rrst
Crst
RST pin
Internal reset
Reset input circuitry
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