參數(shù)資料
型號: T89C51RD2-RLBI-M
廠商: Atmel Corp.
英文描述: 0 to 40MHz Flash Programmable 8-bit Microcontroller
中文描述: 0至40MHz可編程閃存8位微控制器
文件頁數(shù): 95/170頁
文件大小: 1927K
代理商: T89C51RD2-RLBI-M
95
A/T89C51CC01
4129L–CAN–08/05
Time Trigger
Communication (TTC)
and Message Stamping
The T89C51CC01 has a programmable 16-bit Timer (CANTIMH and CANTIML) for
message stamp and TTC.
This CAN Timer starts after the CAN controller is enabled by the ENA bit in the CANG-
CON register.
Two modes in the timer are implemented:
Time Trigger Communication:
Capture of this timer value in the CANTTCH and CANTTCL registers on
Start Of Frame (SOF) or End Of Frame (EOF), depending on the SYNCTTC
bit in the CANGCON register, when the network is configured in TTC by the
TTC bit in the CANGCON register.
Note:
In this mode, CAN
only sends the frame once, even if an error occurs
.
Message Stamping
Capture of this timer value in the CANSTMPH and CANSTMPL registers of
the message object which received or sent the frame.
All messages can be stamps.
The stamping of a received frame occurs when the RxOk flag is set.
The stamping of a sent frame occurs when the TxOk flag is set.
The CAN Timer works in a roll-over from FFFFh to 0000h which serves as a time base.
When the timer roll-over from FFFFh to 0000h, an interrupt is generated if the ETIM bit
in the interrupt enable register IEN1 is set.
Figure 51.
Block Diagram of CAN Timer
EOF on CAN frame
ENA
CANGCON.1
CANTCON
RXOK i
CANSTCH.5
TXOK i
CANSTCH.4
÷
6
Fcan
CLOCK
SOF on CAN frame
TTC
CANGCON.5
SYNCTTC
CANGCON.4
CANTTCH and CANTTCL
CANSTMPH and CANSTMPL
CANTIMH and CANTIML
OVRTIM
CANGIT.5
When 0xFFFF to 0x0000
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