參數(shù)資料
型號： T89C51RD2-DDRC-L
廠商： Atmel Corp.
英文描述： 0 to 40MHz Flash Programmable 8-bit Microcontroller
中文描述： 0至40MHz可編程閃存8位微控制器
文件頁數(shù)： 110/170頁
文件大?。?/td> 1927K
代理商： T89C51RD2-DDRC-L
110
A/T89C51CC01
4129L–CAN–08/05
Table 73.
CANPAGE Register
CANPAGE (S:B1h)
CAN Message Object Page Register
Reset Value = 0000 0000b
Table 74.
CANCONCH Register
CANCONCH (S:B3h)
CAN Message Object Control and DLC Register
No default value after reset
7
6
5
4
3
2
1
0
CHNB 3
CHNB 2
CHNB 1
CHNB 0
AINC
INDX2
INDX1
INDX0
Bit
Number
Bit Mnemonic Description
7-4
CHNB3:0
Selection of Message Object Number
The available numbers are: 0 to 14 (see Figure 44).
3
AINC
Auto Increment of the Index (active low)
0 - auto-increment of the index (default value).
1 - non-auto-increment of the index.
2-0
INDX2:0
Index
Byte location of the data field for the defined message object (see Figure 44).
7
6
5
4
3
2
1
0
CONCH 1
CONCH 0
RPLV
IDE
DLC 3
DLC 2
DLC 1
DLC 0
Bit
Number
Bit Mnemonic Description
7-6
CONCH1:0
Configuration of Message Object
CONCH1 CONCH0
0
0: disable
0
1: Launch transmission
1
0: Enable Reception
1
1: Enable Reception Buffer
Note: The user must re-write the configuration to enable the corresponding bit
in the CANEN1:2 registers.
5
RPLV
Reply Valid
Used in the automatic reply mode after receiving a remote frame
0 - reply not ready.
1 - reply ready and valid.
4
IDE
Identifier Extension
0 - CAN standard rev 2.0 A (ident = 11 bits).
1 - CAN standard rev 2.0 B (ident = 29 bits).
3-0
DLC3:0
Data Length Code
Number of Bytes in the data field of the message.
The range of DLC is from 0 up to 8.
This value is updated when a frame is received (data or remote frame).
If the expected DLC differs from the incoming DLC, a warning appears in the
CANSTCH register.
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參數(shù)描述
T89C51RD2-DDRC-M 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:0 to 40MHz Flash Programmable 8-bit Microcontroller
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T89C51RD2-DDSC-L 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:0 to 40MHz Flash Programmable 8-bit Microcontroller
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