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| 型號(hào)： | T89C51RD2-3CTI-L |
| 廠商： | Atmel Corp. |
| 英文描述： | 0 to 40MHz Flash Programmable 8-bit Microcontroller |
| 中文描述： | 0至40MHz可編程閃存8位微控制器 |
| 文件頁(yè)數(shù)： | 28/170頁(yè) |
| 文件大?。?/td> | 1927K |
| 代理商： | T89C51RD2-3CTI-L |
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28
A/T89C51CC01
4129L–CAN–08/05
External Space
Memory Interface
The external memory interface comprises the external bus (port 0 and port 2) as well as
the bus control signals (RD, WR, and ALE).
Figure 13 shows the structure of the external address bus. P0 carries address A7:0
while P2 carries address A15:8. Data D7:0 is multiplexed with A7:0 on P0. Table 17
describes the external memory interface signals.
Figure 13.
External Data Memory Interface Structure
Table 17.
External Data Memory Interface Signals
External Bus Cycles
This section describes the bus cycles the T89C51CC01 executes to read (see
Figure 14), and write data (see Figure 15) in the external data memory.
External memory cycle takes 6 CPU clock periods. This is equivalent to 12 oscillator
clock period in standard mode or 6 oscillator clock periods in X2 mode. For further infor-
mation on X2 mode.
Slow peripherals can be accessed by stretching the read and write cycles. This is done
using the M0 bit in AUXR register. Setting this bit changes the width of the RD and WR
signals from 3 to 15 CPU clock periods.
For simplicity, the accompanying figures depict the bus cycle waveforms in idealized
form and do not provide precise timing information. For bus cycle timing parameters
refer to the Section “AC Characteristics”.
Signal
Name
Type
Description
Alternative
Function
A15:8
O
Address Lines
Upper address lines for the external bus.
P2.7:0
AD7:0
I/O
Address/Data Lines
Multiplexed lower address lines and data for the external
memory.
P0.7:0
ALE
O
Address Latch Enable
ALE signals indicates that valid address information are available
on lines AD7:0.
-
RD
O
Read
Read signal output to external data memory.
P3.7
WR
O
Write
Write signal output to external memory.
P3.6
RAM
PERIPHERAL
T89C51CC01
P2
P0
AD7:0
A15:8
A7:0
A15:8
D7:0
OE
A7:0
ALE
WR
RD
WR
Latch
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| T89C51RD2-3CTI-M | 0 to 40MHz Flash Programmable 8-bit Microcontroller |
| T89C51RD2-3CVI-L | 0 to 40MHz Flash Programmable 8-bit Microcontroller |
| T89C51RD2-3CVI-M | 0 to 40MHz Flash Programmable 8-bit Microcontroller |
| T89C51RD2-3CWI-L | 0 to 40MHz Flash Programmable 8-bit Microcontroller |
| T89C51RD2-3CWI-M | 0 to 40MHz Flash Programmable 8-bit Microcontroller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| T89C51RD2-3CTI-M | 制造商:ATMEL 制造商全稱(chēng):ATMEL Corporation 功能描述:0 to 40MHz Flash Programmable 8-bit Microcontroller |
| T89C51RD2-3CUC-L | 制造商:ATMEL 制造商全稱(chēng):ATMEL Corporation 功能描述:0 to 40MHz Flash Programmable 8-bit Microcontroller |
| T89C51RD2-3CUC-M | 制造商:ATMEL 制造商全稱(chēng):ATMEL Corporation 功能描述:0 to 40MHz Flash Programmable 8-bit Microcontroller |
| T89C51RD2-3CUI-L | 制造商:ATMEL 制造商全稱(chēng):ATMEL Corporation 功能描述:0 to 40MHz Flash Programmable 8-bit Microcontroller |
| T89C51RD2-3CUI-M | 制造商:ATMEL 制造商全稱(chēng):ATMEL Corporation 功能描述:0 to 40MHz Flash Programmable 8-bit Microcontroller |
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