參數(shù)資料
型號： T89C51RB2-3CSIM
廠商： ATMEL CORP
元件分類： 微控制器/微處理器
英文描述： 8-bit Microcontroller with 16 Kbytes/ 32 Kbytes FLASH
中文描述： 8-BIT, FLASH, 40 MHz, MICROCONTROLLER, PDIP40
封裝： PLASTIC, DIP-40
文件頁數(shù)： 100/170頁
文件大小： 1927K
代理商： T89C51RB2-3CSIM
100
A/T89C51CC01
4129L–CAN–08/05
Registers
Table 58.
CANGCON Register
CANGCON (S:ABh)
CAN General Control Register
Reset Value = 0000 0000b
7
6
5
4
3
2
1
0
ABRQ
OVRQ
TTC
SYNCTTC
AUTOBAUD
TEST
ENA
GRES
Bit
Number
Bit Mnemonic Description
7
ABRQ
Abort Request
Not an auto-resetable bit. A reset of the ENCH bit (message object control
and DLC register) is done for each message object. The pending transmission
communications are immediately aborted but the on-going communication will
be terminated normally, setting the appropriate status flags, TXOK or RXOK.
6
OVRQ
Overload frame request (initiator)
Auto-resetable bit.
Set to send an overload frame after the next received message.
Cleared by the hardware at the beginning of transmission of the overload
frame.
5
TTC
Network in Timer Trigger Communication
set to select node in TTC.
clear to disable TTC features.
4
SYNCTTC
Synchronization of TTC
When this bit is set the TTC timer is caught on the last bit of the End Of
Frame.
When this bit is clear the TTC timer is caught on the Start Of Frame.
This bit is only used in the TTC mode.
3
AUTOBAUD
AUTOBAUD
set to active listening mode.
Clear to disable listening mode
2
TEST
Test mode. The test mode is intended for factory testing and not for customer
use.
1
ENA/STB
Enable/Standby CAN Controller
When this bit is set, it enables the CAN controller and its input clock.
When this bit is clear, the on-going communication is terminated normally and
the CAN controller state of the machine is frozen (the ENCH bit of each
message object does not change).
In the standby mode, the transmitter constantly provides a recessive level; the
receiver is not activated and the input clock is stopped in the CAN controller.
During the disable mode, the registers and the mailbox remain accessible.
Note that two clock periods are needed to start the CAN controller state of the
machine.
0
GRES
General Reset (software reset)
Auto-resetable bit. This reset command is ‘ORed’ with the hardware reset in
order to reset the controller. After a reset, the controller is disabled.
相關(guān)PDF資料
PDF描述
T89C51RD2-3CTC-L 0 to 40MHz Flash Programmable 8-bit Microcontroller
T89C51RD2-3CTC-M 0 to 40MHz Flash Programmable 8-bit Microcontroller
T89C51RC2-3CTCL 8-bit Microcontroller with 16 Kbytes/ 32 Kbytes FLASH
T89C51RB2-3CTCL 8-bit Microcontroller with 16 Kbytes/ 32 Kbytes FLASH
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
T89C51RB2-3CTCL 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:8-bit Microcontroller with 16 Kbytes/ 32 Kbytes FLASH
T89C51RB2-3CTCM 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:8-bit Microcontroller with 16 Kbytes/ 32 Kbytes FLASH
T89C51RB2-3CTIL 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:8-bit Microcontroller with 16 Kbytes/ 32 Kbytes FLASH
T89C51RB2-3CTIM 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:8-bit Microcontroller with 16 Kbytes/ 32 Kbytes FLASH
T89C51RB2-3CWCL 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:8-bit Microcontroller with 16 Kbytes/ 32 Kbytes FLASH
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