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參數(shù)資料
| 型號： | T89C51IC2-SLSIL |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-bit Microcontroller with Flash and I2C Interface |
| 中文描述： | 8-BIT, FLASH, 20 MHz, MICROCONTROLLER, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 77/170頁 |
| 文件大小： | 1927K |
| 代理商： | T89C51IC2-SLSIL |
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77
A/T89C51CC01
4129L–CAN–08/05
Watchdog Timer During
Power-down Mode and
Idle
In Power-down mode the oscillator stops, which means the WDT also stops. While in
Power-down mode, the user does not need to service the WDT. There are 2 methods of
exiting Power-down mode: by a hardware reset or via a level activated external interrupt
which is enabled prior to entering Power-down mode. When Power-down is exited with
hardware reset, the Watchdog is disabled. Exiting Power-down with an interrupt is sig-
nificantly different. The interrupt shall be held low long enough for the oscillator to
stabilize. When the interrupt is brought high, the interrupt is serviced. To prevent the
WDT from resetting the device while the interrupt pin is held low, the WDT is not started
until the interrupt is pulled high. It is suggested that the WDT be reset during the inter-
rupt service for the interrupt used to exit Power-down.
To ensure that the WDT does not overflow within a few states of exiting powerdown, it is
best to reset the WDT just before entering powerdown.
In the Idle mode, the oscillator continues to run. To prevent the WDT from resetting
T89C51CC01 while in Idle mode, the user should always set up a timer that will periodi-
cally exit Idle, service the WDT, and re-enter Idle mode.
Register
Table 54.
WDTPRG Register
WDTPRG
(S:A7h)
Watchdog Timer Duration Programming Register
Reset Value = XXXX X000b
7
6
5
4
3
2
1
0
–
–
–
–
–
S2
S1
S0
Bit
Number
Bit
Mnemonic
Description
7
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
6
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
5
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
3
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
2
S2
Watchdog Timer Duration selection bit 2
Work in conjunction with bit 1 and bit 0.
1
S1
Watchdog Timer Duration selection bit 1
Work in conjunction with bit 2 and bit 0.
0
S0
Watchdog Timer Duration selection bit 0
Work in conjunction with bit 1 and bit 2.
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