參數(shù)資料
型號: T89C51CC02UA-RATIM
廠商: ATMEL CORP
元件分類: 微控制器/微處理器
英文描述: Enhanced 8-bit Microcontroller with CAN Controller and Flash
中文描述: 8-BIT, FLASH, 40 MHz, MICROCONTROLLER, PQFP32
封裝: VQFP-32
文件頁數(shù): 9/170頁
文件大?。?/td> 1927K
代理商: T89C51CC02UA-RATIM
9
A/T89C51CC01
4129L–CAN–08/05
Figure 3.
Port 2 Structure
Notes:
1. Port 2 is precluded from use as general-purpose I/O Ports when as address/data bus
drivers.
2. Port 2 internal strong pull-ups FET (P1 in FiGURE) assist the logic-one output for
memory bus cycle.
When Port 0 and Port 2 are used for an external memory cycle, an internal control signal
switches the output-driver input from the latch output to the internal address/data line.
Read-Modify-Write
Instructions
Some instructions read the latch data rather than the pin data. The latch based instruc-
tions read the data, modify the data and then rewrite the latch. These are called "Read-
Modify-Write" instructions. Below is a complete list of these special instructions (see
Table ). When the destination operand is a Port or a Port bit, these instructions read the
latch rather than the pin:
D
Q
P2.X
LATCH
INTERNAL
BUS
WRITE
TO
LATCH
READ
PIN
READ
LATCH
0
1
P2.x (1)
ADDRESS HIGH/CONTROL
VDD
INTERNAL
PULL-UP (2)
Table 2.
Read-Modify-Write Instructions
Instruction
Description
Example
ANL
logical AND
ANL P1, A
ORL
logical OR
ORL P2, A
XRL
logical EX-OR
XRL P3, A
JBC
jump if bit = 1 and clear bit
JBC P1.1, LABEL
CPL
complement bit
CPL P3.0
INC
increment
INC P2
DEC
decrement
DEC P2
DJNZ
decrement and jump if not zero
DJNZ P3, LABEL
MOV Px.y, C
move carry bit to bit y of Port x
MOV P1.5, C
CLR Px.y
clear bit y of Port x
CLR P2.4
SET Px.y
set bit y of Port x
SET P3.3
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